Default SEL to 1's if SEL=0 (fixes #43)

diff --git a/gram/frontend/wishbone.py b/gram/frontend/wishbone.py
index 44856bd2745fac71d6fce29ba2ff1e85f408b1d2..658bf9df235635147b61b955b675d73ad00afaa5 100644 (file)
--- a/gram/frontend/wishbone.py
+++ b/gram/frontend/wishbone.py
@@ -37,6 +37,12 @@ class gramWishbone(Peripheral, Elaboratable):
 
         ratio_bitmask = Repl(1, log2_int(self.ratio))
 
+        sel = Signal.like(self.bus.sel)
+        with m.If(self.bus.sel == 0):
+            m.d.comb += sel.eq(Repl(1, sel.width))
+        with m.Else():
+            m.d.comb += sel.eq(self.bus.sel)
+
         with m.Switch(self.bus.adr & ratio_bitmask):
             for i in range(self.ratio):
                 with m.Case(i):

diff --git a/gram/test/test_frontend_wishbone.py b/gram/test/test_frontend_wishbone.py
index ff07cc0d16723c1979a7c7ccc21434c5eca2283d..d016d60f081b4973ee7199ed796795e0e54b3644 100644 (file)
--- a/gram/test/test_frontend_wishbone.py
+++ b/gram/test/test_frontend_wishbone.py
@@ -308,3 +308,27 @@ class GramWishboneTestCase(FHDLTestCase):
                 ackCallback=selfirstdword)
 
         runSimulation(dut, process, "test_frontend_wishbone.vcd")
+
+    def test_sel_empty(self):
+        core = FakeGramCore()
+        native_port = core.crossbar.get_native_port()
+        dut = gramWishbone(core, data_width=32, granularity=8)
+
+        def process():
+            # Initialize native port
+            yield native_port.cmd.ready.eq(0)
+            yield native_port.wdata.ready.eq(0)
+            yield native_port.rdata.valid.eq(0)
+
+            def selfirstdword(bus, native_port):
+                self.assertEqual((yield native_port.wdata.we), 0xF)
+
+            yield from self.write_request(bus=dut.bus,
+                native_port=native_port,
+                adr=0,
+                sel=0,
+                value=0xAAAAAAAA,
+                timeout=128,
+                ackCallback=selfirstdword)
+
+        runSimulation(dut, process, "test_frontend_wishbone.vcd")