For include/opcode:

	* mips.h (INSN_ISA5): New.

For opcodes:

	* mips-opc.c (I5): New.
	(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
	madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
	pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ebf79ddd97f23542a302902abae974a24a3c859a..01e881d834c8d1da9239f3dd5e634c95c4c26606 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
+
+       * mips.h (INSN_ISA5): New.
+
 1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com>
 
        * mips.h (OPCODE_IS_MEMBER): New.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 07e0fd7c679edff8b23dc2e46ae52806f60f22b3..8c93d1bd7a3da131c0277d51a3667ea9e7eabc8b 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -308,6 +308,7 @@ struct mips_opcode
 #define INSN_ISA3                  0x00000003
 /* MIPS ISA 4 instruction (R8000).  */
 #define INSN_ISA4                  0x00000004
+#define INSN_ISA5                  0x00000005
 
 /* Chip specific instructions.  These are bitmasks.  */
 /* MIPS R4650 instruction.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bdaaef3a09a02042097a72914e3bf0ecec526d23..5e4e6abf7c19a96d64a81e14aca0222c6101c0a6 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
+
+       * mips-opc.c (I5): New.
+       (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
+       madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
+       pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
+
 Mon Nov 15 19:34:58 1999  Donald Lindsay  <dlindsay@cygnus.com>
 
        * arm-dis.c (print_insn_arm): Added general purpose 'X' format.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 8e68622982d3d6262a77b84b1534221273ccf936..f81f44f3e83ac8b38cd085f975056124261bbcb9 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -76,6 +76,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define I2     INSN_ISA2
 #define I3     INSN_ISA3
 #define I4     INSN_ISA4
+#define I5     INSN_ISA5
 #define P3     INSN_4650
 #define L1     INSN_4010
 #define V1      INSN_4100
@@ -122,14 +123,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"abs",     "d,v",     0,    (int) M_ABS,      INSN_MACRO,     I1      },
 {"abs.s",   "D,V",     0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1      },
 {"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1      },
+{"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5      },
 {"add",     "d,v,t",   0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,     I1      },
 {"add.s",   "D,V,T",   0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1},
 {"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1},
+{"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 {"addi",    "t,r,j",   0x20000000, 0xfc000000, WR_t|RD_s,      I1      },
 {"addiu",   "t,r,j",   0x24000000, 0xfc000000, WR_t|RD_s,      I1      },
 {"addu",    "d,v,t",   0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"addu",    "t,r,I",   0,    (int) M_ADDU_I,   INSN_MACRO,     I1      },
+{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    I5},
 {"and",     "d,v,t",   0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,     I1      },
 {"andi",    "t,r,i",   0x30000000, 0xfc000000, WR_t|RD_s,      I1      },
@@ -218,66 +222,98 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"c.f.d",   "M,S,T",   0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.f.s",   "S,T",     0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.f.s",   "M,S,T",   0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.un.d",  "M,S,T",   0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.un.s",  "S,T",     0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.un.s",  "M,S,T",   0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.eq.d",  "M,S,T",   0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.eq.s",  "S,T",     0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.eq.s",  "M,S,T",   0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ueq.d", "M,S,T",   0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ueq.s", "S,T",     0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ueq.s", "M,S,T",   0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.lt.s",  "M,S,T",   0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.olt.d", "S,T",     0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.olt.d", "M,S,T",   0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.olt.s", "M,S,T",   0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ult.d", "M,S,T",   0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ult.s", "S,T",     0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ult.s", "M,S,T",   0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.le.s",  "M,S,T",   0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.ole.d", "S,T",     0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ole.d", "M,S,T",   0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ole.s", "S,T",     0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ole.s", "M,S,T",   0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ule.d", "M,S,T",   0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ule.s", "S,T",     0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ule.s", "M,S,T",   0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.sf.d",  "M,S,T",   0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.sf.s",  "S,T",     0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.sf.s",  "M,S,T",   0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ngle.d","M,S,T",   0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ngle.s","S,T",     0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ngle.s","M,S,T",   0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.seq.d", "M,S,T",   0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.seq.s", "S,T",     0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.seq.s", "M,S,T",   0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ngl.d", "M,S,T",   0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ngl.s", "S,T",     0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ngl.s", "M,S,T",   0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.lt.d",  "M,S,T",   0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
+{"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.nge.d", "M,S,T",   0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.nge.s", "S,T",     0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.nge.s", "M,S,T",   0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.le.d",  "M,S,T",   0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
+{"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ngt.d", "M,S,T",   0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ngt.s", "S,T",     0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ngt.s", "M,S,T",   0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
+{"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I5      },
 {"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3|M1        },
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3      },
@@ -301,8 +337,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"cvt.s.l", "D,S",     0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"cvt.s.d", "D,S",     0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I1      },
 {"cvt.s.w", "D,S",     0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1      },
+{"cvt.s.pl","D,S",     0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
+{"cvt.s.pu","D,S",     0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    I5      },
 {"cvt.w.d", "D,S",     0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1      },
 {"cvt.w.s", "D,S",     0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1      },
+{"cvt.ps.s","D,V,T",   0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,     I3      },
 {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 {"dadd",    "t,r,I",   0,    (int) M_DADD_I,   INSN_MACRO,     I3      },
@@ -456,6 +495,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"lld",            "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,  I3      },
 {"lld",     "t,A(b)",  0,    (int) M_LLD_AB,   INSN_MACRO,     I3      },
 {"lui",     "t,u",     0x3c000000, 0xffe00000, WR_t,           I1      },
+{"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b,     I5      },
 {"lw",      "t,o(b)",  0x8c000000, 0xfc000000, LDD|RD_b|WR_t,  I1      },
 {"lw",      "t,A(b)",  0,    (int) M_LW_AB,    INSN_MACRO,     I1      },
 {"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1      },
@@ -487,6 +527,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"madu",    "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,      P3      },
 {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
+{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"madd",    "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
 {"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,             G1|M1   },
 {"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1      },
@@ -503,9 +544,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,     I1      },
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1      },
+{"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5      },
 {"movf",    "d,s,N",   0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|M1},
 {"movf.d",  "D,S,N",   0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movf.s",  "D,S,N",   0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
+{"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5      },
 {"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movn.d",  "D,S,t",   0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
@@ -513,6 +556,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"movt",    "d,s,N",   0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|M1   },
 {"movt.d",  "D,S,N",   0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
 {"movt.s",  "D,S,N",   0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
+{"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I5},
 {"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1    },
 {"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
@@ -520,6 +564,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 /* move is at the top of the table.  */
 {"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
+{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"msub",    "s,t",     0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
 {"msubu",   "s,t",     0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1        },
 {"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   I1      },
@@ -531,6 +576,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mtlo",    "s",       0x00000013, 0xfc1fffff, RD_s|WR_LO,     I1      },
 {"mul.d",   "D,V,T",   0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },
 {"mul.s",   "D,V,T",   0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
+{"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
 {"mul",     "d,v,t",   0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO,P3},
 {"mul",     "d,v,t",   0,    (int) M_MUL,      INSN_MACRO,     I1      },
 {"mul",     "d,v,I",   0,    (int) M_MUL_I,    INSN_MACRO,     I1      },
@@ -546,10 +592,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"negu",    "d,w",     0x00000023, 0xffe007ff, WR_d|RD_t,      I1      }, /* subu 0 */
 {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1      },
+{"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,I5       },
 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
+{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
+{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I5      },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,     I1      },
@@ -558,10 +607,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO,     I1      },
 {"ori",     "t,r,i",   0x34000000, 0xfc000000, WR_t|RD_s,      I1      },
 
+{"pll.ps",  "D,V,T",   0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
+{"plu.ps",  "D,V,T",   0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 
 {"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3|M1   },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 
+{"pul.ps",  "D,V,T",   0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
+{"puu.ps",  "D,V,T",   0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5},
 
 {"recip.d", "D,S",     0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4      },
 {"recip.s", "D,S",     0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4      },
@@ -653,9 +706,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,     I1      },
 {"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I1      },     
 {"sub.s",   "D,V,T",   0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    I1      },
+{"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    I5      },
 {"subu",    "d,v,t",   0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"subu",    "d,v,I",   0,    (int) M_SUBU_I,   INSN_MACRO,     I1      },
 {"suspend", "",         0x42000022, 0xffffffff,        0,              V1      },
+{"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     I5      },
 {"sw",      "t,o(b)",  0xac000000, 0xfc000000, SM|RD_t|RD_b,   I1      },
 {"sw",      "t,A(b)",  0,    (int) M_SW_AB,    INSN_MACRO,     I1      },
 {"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,  I1      },