freedreno/ir3: add dev ptr to ir3_compiler
authorRob Clark <robclark@freedesktop.org>
Tue, 1 Mar 2016 22:31:21 +0000 (17:31 -0500)
committerRob Clark <robclark@freedesktop.org>
Wed, 2 Mar 2016 00:20:33 +0000 (19:20 -0500)
And use this for allocating bo's to hold the shader binary, rather than
accessing the dev via ctx ptr.  One step towards making shaders sharable
across contexts.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
src/gallium/drivers/freedreno/a3xx/fd3_screen.c
src/gallium/drivers/freedreno/a4xx/fd4_screen.c
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
src/gallium/drivers/freedreno/ir3/ir3_compiler.c
src/gallium/drivers/freedreno/ir3/ir3_compiler.h
src/gallium/drivers/freedreno/ir3/ir3_shader.c

index 722fe36020296256fa89fa3010da24de18582f10..4aea2fe0f37e7fccf54f9dc44440d2683263aa43 100644 (file)
@@ -106,7 +106,7 @@ fd3_screen_init(struct pipe_screen *pscreen)
 {
        struct fd_screen *screen = fd_screen(pscreen);
        screen->max_rts = A3XX_MAX_RENDER_TARGETS;
-       screen->compiler = ir3_compiler_create(screen->gpu_id);
+       screen->compiler = ir3_compiler_create(screen->dev, screen->gpu_id);
        pscreen->context_create = fd3_context_create;
        pscreen->is_format_supported = fd3_screen_is_format_supported;
 }
index b2a69cca56c5dfdb57c6e2c678fe11dff71d6339..c193f361e4c84a2ad366df683c62a441db35ff2f 100644 (file)
@@ -105,7 +105,7 @@ fd4_screen_init(struct pipe_screen *pscreen)
 {
        struct fd_screen *screen = fd_screen(pscreen);
        screen->max_rts = A4XX_MAX_RENDER_TARGETS;
-       screen->compiler = ir3_compiler_create(screen->gpu_id);
+       screen->compiler = ir3_compiler_create(screen->dev, screen->gpu_id);
        pscreen->context_create = fd4_context_create;
        pscreen->is_format_supported = fd4_screen_is_format_supported;
 }
index 481859efb174b939c0fc2bcaabb694a42e784c13..7ae4e94f0b349afc0e0b79b23e91ebcc9ecdcd84 100644 (file)
@@ -233,7 +233,7 @@ int main(int argc, char **argv)
                tgsi_dump(toks, 0);
 
        nir_shader *nir = ir3_tgsi_to_nir(toks);
-       s.compiler = ir3_compiler_create(gpu_id);
+       s.compiler = ir3_compiler_create(NULL, gpu_id);
        s.nir = ir3_optimize_nir(&s, nir, NULL);
 
        v.key = key;
index 7c8eccb54e1f1bcb8a3ff72f86722381e0ecd0f4..37ad73380ab863ec79c829e74ced8765756f5b31 100644 (file)
 
 #include "ir3_compiler.h"
 
-struct ir3_compiler * ir3_compiler_create(uint32_t gpu_id)
+struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id)
 {
        struct ir3_compiler *compiler = rzalloc(NULL, struct ir3_compiler);
+       compiler->dev = dev;
        compiler->gpu_id = gpu_id;
        compiler->set = ir3_ra_alloc_reg_set(compiler);
        return compiler;
index 697afeba61a6651744f382b4bb7c66f846573229..0ad689ca1e744df4305cfddf098ffa7bf588780c 100644 (file)
 struct ir3_ra_reg_set;
 
 struct ir3_compiler {
+       struct fd_device *dev;
        uint32_t gpu_id;
        struct ir3_ra_reg_set *set;
        uint32_t shader_count;
 };
 
-struct ir3_compiler * ir3_compiler_create(uint32_t gpu_id);
+struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id);
 void ir3_compiler_destroy(struct ir3_compiler *compiler);
 
 int ir3_compile_shader_nir(struct ir3_compiler *compiler,
index 7d17f426ad352553417e007d68ae69e9ca06cb2e..26106072b5ab65615ff1e4e89c5fec0891fe5452 100644 (file)
@@ -127,14 +127,14 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 static void
 assemble_variant(struct ir3_shader_variant *v)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
-       uint32_t gpu_id = v->shader->compiler->gpu_id;
+       struct ir3_compiler *compiler = v->shader->compiler;
+       uint32_t gpu_id = compiler->gpu_id;
        uint32_t sz, *bin;
 
        bin = ir3_shader_assemble(v, gpu_id);
        sz = v->info.sizedwords * 4;
 
-       v->bo = fd_bo_new(ctx->dev, sz,
+       v->bo = fd_bo_new(compiler->dev, sz,
                        DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
                        DRM_FREEDRENO_GEM_TYPE_KMEM);