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rs6000-c.c (altivec_overloaded_builtins): Add ALTIVEC_BUILTIN_VMULESW...
authorCarl Love <cel@us.ibm.com>
Sat, 22 Jul 2017 00:16:26 +0000 (00:16 +0000)
committerCarl Love <carll@gcc.gnu.org>
Sat, 22 Jul 2017 00:16:26 +0000 (00:16 +0000)
gcc/ChangeLog:

2017-07-21  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries.
* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin,
builtin_function_type): Add ALTIVEC_BUILTIN_* case statements.
* config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW,
VMULOSW): New enum "unspec" values.
(altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw,
altivec_vmulosw): New patterns.
* config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW,
VMULOSW): Add definitions.

gcc/testsuite/ChangeLog:

2017-07-21  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-2.c (vmulosh, vmulouh, vmulesh,
vmuleuh): Fix scan-assembler-times should check for word not half word
instructions.

From-SVN: r250450

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/altivec.md patch | blob | history
gcc/config/rs6000/rs6000-builtin.def patch | blob | history
gcc/config/rs6000/rs6000-c.c patch | blob | history
gcc/config/rs6000/rs6000.c patch | blob | history
gcc/testsuite/ChangeLog patch | blob | history
gcc/testsuite/gcc.target/powerpc/builtins-3.c patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cc18d59564e78142c7d65aed0418524c368a666e..8ec7a798b1d066131af5b9b8f10f5d691b562e4e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2017-07-21  Carl Love  <cel@us.ibm.com>
+
+       * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+       ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW,
+       ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries.
+       * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin,
+       builtin_function_type): Add ALTIVEC_BUILTIN_* case statements.
+       * config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW,
+       VMULOSW): New enum "unspec" values.
+       (altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw,
+       altivec_vmulosw): New patterns.
+       * config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW,
+       VMULOSW): Add definitions.
+
 2017-07-21  Jim Wilson  <jim.wilson@linaro.org>
 
        * config/aarch64/aarch64-cores.def (falkor): Add AARCH64_FL_RDMA.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 91c56512308c64ccd3789284c21cb9cb5a8a4b63..c14cb92f0f32bf87d4c20be7bd67deee4ac5e910 100644 (file)
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -36,10 +36,14 @@
    UNSPEC_VMULESB
    UNSPEC_VMULEUH
    UNSPEC_VMULESH
+   UNSPEC_VMULEUW
+   UNSPEC_VMULESW
    UNSPEC_VMULOUB
    UNSPEC_VMULOSB
    UNSPEC_VMULOUH
    UNSPEC_VMULOSH
+   UNSPEC_VMULOUW
+   UNSPEC_VMULOSW
    UNSPEC_VPKPX
    UNSPEC_VPACK_SIGN_SIGN_SAT
    UNSPEC_VPACK_SIGN_UNS_SAT
@@ -1538,6 +1542,41 @@
   "vmulosh %0,%1,%2"
   [(set_attr "type" "veccomplex")])
 
+(define_insn "altivec_vmuleuw"
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
+       (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
+                     (match_operand:V4SI 2 "register_operand" "v")]
+                    UNSPEC_VMULEUW))]
+  "TARGET_P8_VECTOR"
+  "vmuleuw %0,%1,%2"
+  [(set_attr "type" "veccomplex")])
+
+(define_insn "altivec_vmulouw"
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
+       (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
+                     (match_operand:V4SI 2 "register_operand" "v")]
+                    UNSPEC_VMULOUW))]
+  "TARGET_P8_VECTOR"
+  "vmulouw %0,%1,%2"
+  [(set_attr "type" "veccomplex")])
+
+(define_insn "altivec_vmulesw"
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
+       (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
+                     (match_operand:V4SI 2 "register_operand" "v")]
+                    UNSPEC_VMULESW))]
+  "TARGET_P8_VECTOR"
+  "vmulesw %0,%1,%2"
+  [(set_attr "type" "veccomplex")])
+
+(define_insn "altivec_vmulosw"
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
+       (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v")
+                     (match_operand:V4SI 2 "register_operand" "v")]
+                    UNSPEC_VMULOSW))]
+  "TARGET_P8_VECTOR"
+  "vmulosw %0,%1,%2"
+  [(set_attr "type" "veccomplex")])
 
 ;; Vector pack/unpack
 (define_insn "altivec_vpkpx"
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index bf2c90b49fbf6f0ece8aaf04694c83f00ab86e13..e161423662cb551aeab270333068708463a2a662 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1031,10 +1031,14 @@ BU_ALTIVEC_2 (VMULEUB,        "vmuleub",        CONST,  vec_widen_umult_even_v16qi)
 BU_ALTIVEC_2 (VMULESB,       "vmulesb",        CONST,  vec_widen_smult_even_v16qi)
 BU_ALTIVEC_2 (VMULEUH,       "vmuleuh",        CONST,  vec_widen_umult_even_v8hi)
 BU_ALTIVEC_2 (VMULESH,       "vmulesh",        CONST,  vec_widen_smult_even_v8hi)
+BU_ALTIVEC_2 (VMULEUW,       "vmuleuw",        CONST,  altivec_vmuleuw)
+BU_ALTIVEC_2 (VMULESW,       "vmulesw",        CONST,  altivec_vmulesw)
 BU_ALTIVEC_2 (VMULOUB,       "vmuloub",        CONST,  vec_widen_umult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOSB,       "vmulosb",        CONST,  vec_widen_smult_odd_v16qi)
 BU_ALTIVEC_2 (VMULOUH,       "vmulouh",        CONST,  vec_widen_umult_odd_v8hi)
 BU_ALTIVEC_2 (VMULOSH,       "vmulosh",        CONST,  vec_widen_smult_odd_v8hi)
+BU_ALTIVEC_2 (VMULOUW,       "vmulouw",        CONST,  altivec_vmulouw)
+BU_ALTIVEC_2 (VMULOSW,       "vmulosw",        CONST,  altivec_vmulosw)
 BU_ALTIVEC_2 (VNOR,          "vnor",           CONST,  norv4si3)
 BU_ALTIVEC_2 (VOR,           "vor",            CONST,  iorv4si3)
 BU_ALTIVEC_2 (VPKUHUM,       "vpkuhum",        CONST,  altivec_vpkuhum)
@@ -1353,12 +1357,16 @@ BU_ALTIVEC_OVERLOAD_2 (VMRGLH,     "vmrglh")
 BU_ALTIVEC_OVERLOAD_2 (VMRGLW,    "vmrglw")
 BU_ALTIVEC_OVERLOAD_2 (VMULESB,           "vmulesb")
 BU_ALTIVEC_OVERLOAD_2 (VMULESH,           "vmulesh")
+BU_ALTIVEC_OVERLOAD_2 (VMULESW,           "vmulesw")
 BU_ALTIVEC_OVERLOAD_2 (VMULEUB,           "vmuleub")
 BU_ALTIVEC_OVERLOAD_2 (VMULEUH,           "vmuleuh")
+BU_ALTIVEC_OVERLOAD_2 (VMULEUW,           "vmuleuw")
 BU_ALTIVEC_OVERLOAD_2 (VMULOSB,           "vmulosb")
 BU_ALTIVEC_OVERLOAD_2 (VMULOSH,           "vmulosh")
+BU_ALTIVEC_OVERLOAD_2 (VMULOSW,           "vmulosw")
 BU_ALTIVEC_OVERLOAD_2 (VMULOUB,           "vmuloub")
 BU_ALTIVEC_OVERLOAD_2 (VMULOUH,           "vmulouh")
+BU_ALTIVEC_OVERLOAD_2 (VMULOUW,           "vmulouw")
 BU_ALTIVEC_OVERLOAD_2 (VPKSHSS,           "vpkshss")
 BU_ALTIVEC_OVERLOAD_2 (VPKSHUS,           "vpkshus")
 BU_ALTIVEC_OVERLOAD_2 (VPKSWSS,           "vpkswss")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 2a3612607593b80ce46d4e2db18ae33b7027fe8a..937cda0aa2ae6838ad6c159d95507ebf030c844a 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -2232,9 +2232,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
     RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH,
+  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH,
+  { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB,
@@ -2251,9 +2251,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
+  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW,
     RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
-  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH,
+  { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW,
     RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 988926b8d5996e9dbc47fe11b5b92fc9ae5f58c1..d6be72b6a29893966605630cd6318abcaa4cd9f0 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -18065,8 +18065,10 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
       /* unsigned 2 argument functions.  */
     case ALTIVEC_BUILTIN_VMULEUB:
     case ALTIVEC_BUILTIN_VMULEUH:
+    case ALTIVEC_BUILTIN_VMULEUW:
     case ALTIVEC_BUILTIN_VMULOUB:
     case ALTIVEC_BUILTIN_VMULOUH:
+    case ALTIVEC_BUILTIN_VMULOUW:
     case CRYPTO_BUILTIN_VCIPHER:
     case CRYPTO_BUILTIN_VCIPHERLAST:
     case CRYPTO_BUILTIN_VNCIPHER:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1b5cc63a7819b5f1e17b2592f82242d8c1503f32..b36cd5e6778a05c30e73c0e7181d5018d58f2a40 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2017-07-21  Carl Love  <cel@us.ibm.com>
+
+       * gcc.target/powerpc/builtins-2.c (vmulosh, vmulouh, vmulesh,
+       vmuleuh): Fix scan-assembler-times should check for word not half word
+       instructions.
+
 2017-07-21  Jim Wilson  <jim.wilson@linaro.org>
 
        * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Delete
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index e0e3714dc54cfad7ed23dab8655d1b1b3f63fbc2..00fa6ec0274d9551db349ae799c3de07323acba9 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -236,8 +236,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
 /* { dg-final { scan-assembler-times "xvnegsp"  1 } } */
 /* { dg-final { scan-assembler-times "xvnegdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"     4 } } */
-/* { dang-remove { scan-assembler-times "vmulosw"  1 } } */
-/* { dang-remove  { scan-assembler-times "vmulouw"  1 } } */
-/* { dang-remove  { scan-assembler-times "vmulesw"  1 } } */
-/* { dang-remove  { scan-assembler-times "vmuleuw"  1 } } */
+/* { dg-final { scan-assembler-times "vmulosw"  1 } } */
+/* { dg-final { scan-assembler-times "vmulouw"  1 } } */
+/* { dg-final { scan-assembler-times "vmulesw"  1 } } */
+/* { dg-final { scan-assembler-times "vmuleuw"  1 } } */
 /* { dg-final { scan-assembler-times "xxsldwi"  8 } } */