mov %2,%0\;add %1,%0"
[(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
-(define_expand "adddi3"
- [(set (reg:DI 0) (match_operand:DI 1 "register_operand" ""))
- (set (reg:DI 2) (match_operand:DI 2 "nonmemory_operand" ""))
- (set (reg:DI 0) (plus:DI (reg:DI 0) (reg:DI 2)))
- (set (match_operand:DI 0 "register_operand" "") (reg:DI 0))]
- ""
- "
-{
- if (GET_CODE (operands[2]) == CONST_INT)
- {
- rtx reg0 = gen_rtx (REG, DImode, 0);
-
- emit_move_insn (reg0, operands[1]);
- emit_insn (gen_adddi3_const (operands[2]));
- emit_move_insn (operands[0], reg0);
- DONE;
- }
-}")
-
-;; The general adddi3 pattern.
-(define_insn ""
- [(set (reg:DI 0) (plus:DI (reg:DI 0) (reg:DI 2)))]
- ""
- "add d2,d0\;addc d3,d1"
- [(set_attr "cc" "clobber")])
-
-;; adddi3 with on operand being a constant.
-(define_insn "adddi3_const"
- [(set (reg:DI 0)
- (plus:DI (reg:DI 0) (match_operand:DI 0 "const_int_operand" "i")))
- (clobber (reg:DI 2))]
- ""
- "*
-{
- long value = INTVAL (operands[0]);
-
- if (value < 0)
- return \"mov -1,d2\;add %0,d0\;addc d2,d1\";
- else
- return \"clr d2\;add %0,d0\;addc d2,d1\";
-}"
- [(set_attr "cc" "clobber")])
;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------
DONE;
}")
-(define_expand "subdi3"
- [(set (reg:DI 0) (match_operand:DI 1 "register_operand" ""))
- (set (reg:DI 2) (match_operand:DI 2 "nonmemory_operand" ""))
- (set (reg:DI 0) (minus:DI (reg:DI 0) (reg:DI 2)))
- (set (match_operand:DI 0 "register_operand" "") (reg:DI 0))]
- ""
- "")
-
-(define_insn ""
- [(set (reg:DI 0) (minus:DI (reg:DI 0) (reg:DI 2)))]
- ""
- "sub d2,d0\;subc d3,d1"
- [(set_attr "cc" "clobber")])
-
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------