projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
26e461f
)
Tweak
author
Eddie Hung
<eddie@fpgeh.com>
Tue, 23 Apr 2019 00:59:56 +0000
(17:59 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Tue, 23 Apr 2019 00:59:56 +0000
(17:59 -0700)
techlibs/xilinx/cells_map.v
patch
|
blob
|
history
diff --git
a/techlibs/xilinx/cells_map.v
b/techlibs/xilinx/cells_map.v
index 10dbb8b9a077a13f0b91e2d8e5efe3d5b84dd4e4..4275c03e6d17734988c8a943d347f291bda41e6e 100644
(file)
--- a/
techlibs/xilinx/cells_map.v
+++ b/
techlibs/xilinx/cells_map.v
@@
-179,7
+179,7
@@
module \$shiftx (A, B, Y);
assign A_i[i] = A[i*2];
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end
- else if (B_WIDTH < 3 || A_WIDTH
== 2**2
) begin
+ else if (B_WIDTH < 3 || A_WIDTH
<= 4
) begin
wire _TECHMAP_FAIL_ = 1;
end
else if (B_WIDTH == 3) begin