use LiteScope (replace Miscope)

diff --git a/README b/README
index 881bf1be6882c43e7c8c1dd678bea61ae773afe1..9538a0eb71afe56a0adbc87a473e1ad14162226e 100644 (file)
--- a/README
+++ b/README
@@ -87,9 +87,9 @@ devel [AT] lists.m-labs.hk.
   python3 setup.py install
   cd ..
 
-3. Obtain Miscope and install it:
-  git clone https://github.com/m-labs/miscope
-  cd miscope
+3. Obtain LiteScope and install it:
+  git clone https://github.com/m-labs/litescope
+  cd litescope
   python3 setup.py install
   cd ..
 

diff --git a/make.py b/make.py
index 8d5a44397d23e5bfe2f05466fe4543393bea4d35..401d6a2dd35ec6c9273689d402fa712a7a201004 100644 (file)
--- a/make.py
+++ b/make.py
@@ -19,7 +19,7 @@ def _import(default, name):
 def _get_args():
        parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
                description="""\
-LiteSATA verilog rtl generator - based on Migen.
+LiteSATA - based on Migen.
 
 This program builds and/or loads LiteSATA components.
 One or several actions can be specified:

diff --git a/targets/bist.py b/targets/bist.py
index 03cf31eda66af24e257447bf39c54e47fd62bd77..1872356ee498e6c8a1281291f5f6c4a409d46c47 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -10,7 +10,10 @@ from migen.bank.description import *
 
 from misoclib import identifier
 
-from miscope import MiLa, Term, UART2Wishbone
+from litescope.common import *
+from litescope.bridge.uart2wb import LiteScopeUART2WB
+from litescope.frontend.la import LiteScopeLA
+from litescope.core.trigger import LiteScopeTerm
 
 from litesata.common import *
 from litesata.phy import LiteSATAPHY
@@ -56,19 +59,19 @@ class GenSoC(Module):
        csr_base = 0x00000000
        csr_data_width = 32
        csr_map = {
-               "uart2wb":                      0,
-               "identifier":           2,
+               "bridge":                       0,
+               "identifier":           1,
        }
        interrupt_map = {}
        cpu_type = None
        def __init__(self, platform, clk_freq):
                self.clk_freq = clk_freq
                # UART <--> Wishbone bridge
-               self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
+               self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
 
                # CSR bridge   0x00000000 (shadow @0x00000000)
                self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
-               self._wb_masters = [self.uart2wb.wishbone]
+               self._wb_masters = [self.bridge.wishbone]
                self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
                self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
 
@@ -134,7 +137,7 @@ class BISTSoC(GenSoC, AutoCSR):
        }
        csr_map.update(GenSoC.csr_map)
 
-       def __init__(self, platform, export_mila=False):
+       def __init__(self, platform, export_conf=False):
                clk_freq = 166*1000000
                GenSoC.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
@@ -149,11 +152,11 @@ class BISTSoC(GenSoC, AutoCSR):
 
 class BISTSoCDevel(BISTSoC, AutoCSR):
        csr_map = {
-               "mila":                 11
+               "la":                   10
        }
        csr_map.update(BISTSoC.csr_map)
-       def __init__(self, platform, export_mila=False):
-               BISTSoC.__init__(self, platform, export_mila)
+       def __init__(self, platform, export_conf=False):
+               BISTSoC.__init__(self, platform, export_conf)
 
                self.sata_core_link_rx_fsm_state = Signal(4)
                self.sata_core_link_tx_fsm_state = Signal(4)
@@ -199,11 +202,10 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                        self.sata_core_command_tx_fsm_state,
                )
 
-               self.submodules.mila = MiLa(depth=2048, dat=Cat(*debug))
-               self.mila.add_port(Term)
-               if export_mila:
-                       mila_filename = os.path.join("test", "mila.csv")
-                       self.mila.export(self, debug, mila_filename)
+               self.submodules.la = LiteScopeLA(depth=2048, dat=Cat(*debug))
+               self.la.add_port(LiteScopeTerm)
+               if export_conf:
+                       self.la.export(self, debug,"./test/la.csv")
 
        def do_finalize(self):
                BISTSoC.do_finalize(self)

diff --git a/test/config.py b/test/config.py
index 5b274b23829b82333645f7995cea528f87aca16f..44d8fcee479971f3b15f0ee2bd4514db9c11290e 100644 (file)
--- a/test/config.py
+++ b/test/config.py
@@ -1,4 +1,4 @@
-from miscope.host.uart2wishbone import Uart2Wishbone
+from litescope.host.driver import LiteScopeUART2WBDriver
 
 csr_csv_file = "./csr.csv"
 busword = 32
@@ -6,4 +6,4 @@ debug_wb = False
 
 com = 2
 baud = 921600
-wb = Uart2Wishbone(com, baud, csr_csv_file, busword, debug_wb)
\ No newline at end of file
+wb = LiteScopeUART2WBDriver(com, baud, csr_csv_file, busword, debug_wb)
\ No newline at end of file

diff --git a/test/test_link.py b/test/test_link.py
index de8013cc23b42375873ecf23b1bf13332b23f4db..dfa7d4c5d84dcda2624ffa18aa5f87fdb08928a5 100644 (file)
--- a/test/test_link.py
+++ b/test/test_link.py
@@ -2,9 +2,9 @@ import sys
 from config import *
 from tools import *
 from bist import *
-from miscope.host.drivers import MiLaDriver
+from litescope.host.driver import LiteScopeLADriver
 
-mila = MiLaDriver(wb.regs, "mila")
+la = LiteScopeLADriver(wb.regs, "la")
 identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
 generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
 checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
@@ -41,24 +41,24 @@ conditions["id_pio_setup"] = {
        "source_source_payload_data" : primitives["X_RDY"],
 }
 
-mila.prog_term(port=0, cond=conditions[sys.argv[1]])
-mila.prog_sum("term")
+la.prog_term(port=0, cond=conditions[sys.argv[1]])
+la.prog_sum("term")
 
 # Trigger / wait / receive
-mila.trigger(offset=512, length=2000)
+la.trigger(offset=512, length=2000)
 
 #identify.run()
 generator.run(0, 2, 1, 0)
 #checker.run(0, 2, 1, 0)
-mila.wait_done()
+la.wait_done()
 
-mila.read()
-mila.export("dump.vcd")
+la.read()
+la.export("dump.vcd")
 ###
 wb.close()
 
 f = open("dump_link.txt", "w")
-data = link_trace(mila,
+data = link_trace(la,
        tx_data_name="sink_sink_payload_data",
        rx_data_name="source_source_payload_data"
 )