gallium: add PIPE_CAP_MAX_VARYINGS
authorKarol Herbst <karolherbst@gmail.com>
Fri, 25 Aug 2017 17:22:03 +0000 (19:22 +0200)
committerIlia Mirkin <imirkin@alum.mit.edu>
Fri, 8 Feb 2019 02:51:45 +0000 (21:51 -0500)
Some NVIDIA hardware can accept 128 fragment shader input components,
but only have up to 124 varying-interpolated input components. We add a
new cap to express this cleanly. For most drivers, this will have the
same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader.

Fixes KHR-GL45.limits.max_fragment_input_components

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
[imirkin: rebased, improved docs/commit message]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
19 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/panfrost/pan_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_get.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/v3d/v3d_screen.c
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h
src/mesa/state_tracker/st_extensions.c

index 8bf4a1ab54b17f3ef500df65526e5263a5e3ce41..85ca5e1f5cea71f92d79c7cdf9d3fee7c046fc76 100644 (file)
@@ -488,6 +488,10 @@ The integer capabilities:
   supports switching the format between sRGB and linear for a surface that is
   used as destination in draw and blit calls.
 * ``PIPE_CAP_NIR_COMPACT_ARRAYS``: True if the compiler backend supports NIR's compact array feature, for all shader stages.
+* ``PIPE_CAP_MAX_VARYINGS``: The maximum number of fragment shader
+  varyings. This will generally correspond to
+  ``PIPE_SHADER_CAP_MAX_INPUTS`` for the fragment shader, but in some
+  cases may be a smaller number.
 
 .. _pipe_capf:
 
index fd32023252890ed36bca4d9342a5073054b15ef3..35dcac1409bce946df449062b70e57e214aeb239 100644 (file)
@@ -360,6 +360,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
       return 0;
 
+   case PIPE_CAP_MAX_VARYINGS:
+      return screen->specs.max_varyings;
+
    case PIPE_CAP_PCI_GROUP:
    case PIPE_CAP_PCI_BUS:
    case PIPE_CAP_PCI_DEVICE:
index e596a4e84620f4d1812825c6a3c6bb5819baef08..c3b08ab0e0fdf0fbd23c94ed8e33f76c10fb49bb 100644 (file)
@@ -317,6 +317,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_VIEWPORTS:
                return 1;
 
+       case PIPE_CAP_MAX_VARYINGS:
+               return 16;
+
        case PIPE_CAP_SHAREABLE_SHADERS:
        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
        /* manage the variants for these ourself, to avoid breaking precompile: */
index a7b4a43c0153ef9965f22b09d7740f691b0bf801..78707c66e624d9c09c6c34934f1007d5e47131f2 100644 (file)
@@ -402,6 +402,8 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
       return 0;
    case PIPE_CAP_ENDIANNESS:
       return PIPE_ENDIAN_LITTLE;
+   case PIPE_CAP_MAX_VARYINGS:
+      return 10;
 
    case PIPE_CAP_VENDOR_ID:
       return 0x8086;
index c95016a6cbef6d7610c707194ba7440061a08640..b55b4a3c4feb010c83f8e1449e0c1cb83cfcd790 100644 (file)
@@ -310,6 +310,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 1;
    case PIPE_CAP_CLEAR_TEXTURE:
       return 1;
+   case PIPE_CAP_MAX_VARYINGS:
+      return 32;
    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
index 2b69a8f696824aeaa8d30ea13a50e31d084eb2ce..53551ebc037d01b4c06b8e9406f6e4be41078806 100644 (file)
@@ -79,6 +79,9 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return 2048;
    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
       return 8 * 1024 * 1024;
+   case PIPE_CAP_MAX_VARYINGS:
+      return 8;
+
    /* supported capabilities */
    case PIPE_CAP_ANISOTROPIC_FILTER:
    case PIPE_CAP_POINT_SPRITE:
index 85cb016e3c212d8d53ec7a359df92fe3f8ab25cf..8e65eaf50b1cacb088b028fd18ef1a078a369074 100644 (file)
@@ -156,6 +156,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return NV50_MAX_WINDOW_RECTANGLES;
    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
       return 16 * 1024 * 1024;
+   case PIPE_CAP_MAX_VARYINGS:
+      return 15;
 
    /* supported caps */
    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
index 6a79fd9a9032c552a72b5871dda47e66ff352218..4a289557e3b88766fe694816ebf404823a7814ca 100644 (file)
@@ -182,6 +182,13 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return class_3d >= GM200_3D_CLASS ? 8 : 0;
    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
       return 64 * 1024 * 1024;
+   case PIPE_CAP_MAX_VARYINGS:
+      /* NOTE: These only count our slots for GENERIC varyings.
+       * The address space may be larger, but the actual hard limit seems to be
+       * less than what the address space layout permits, so don't add TEXCOORD,
+       * COLOR, etc. here.
+       */
+      return 0x1f0 / 16;
 
    /* supported caps */
    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -394,18 +401,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
       return 16;
    case PIPE_SHADER_CAP_MAX_INPUTS:
-      if (shader == PIPE_SHADER_VERTEX)
-         return 32;
-      /* NOTE: These only count our slots for GENERIC varyings.
-       * The address space may be larger, but the actual hard limit seems to be
-       * less than what the address space layout permits, so don't add TEXCOORD,
-       * COLOR, etc. here.
-       */
-      if (shader == PIPE_SHADER_FRAGMENT)
-         return 0x1f0 / 16;
-      /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
-       * and excludes 0x60 per-patch inputs.
-       */
       return 0x200 / 16;
    case PIPE_SHADER_CAP_MAX_OUTPUTS:
       return 32;
index 5ee3b4c6006795ccdbd7202ac83b1e7599e26238..3590b608818af90868ab55d669e9c4b4c397c240 100644 (file)
@@ -250,6 +250,9 @@ panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
                 return 4;
 
+        case PIPE_CAP_MAX_VARYINGS:
+                return 16;
+
         default:
                 return u_pipe_screen_get_param_defaults(screen, param);
         }
index 19d3a1bae3028b479c158b7bf871737180c176a8..be0b475e5efc987f5c39a4ff1c9cb904d4ac15ff 100644 (file)
@@ -304,6 +304,9 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
             return 2048;
 
+        case PIPE_CAP_MAX_VARYINGS:
+            return 10;
+
         case PIPE_CAP_VENDOR_ID:
                 return 0x1002;
         case PIPE_CAP_DEVICE_ID:
index ade1a94ab320e0b4f87cf22146bf48f3051b044e..41a878ab9d249615adbdc2b16e73504a2a09ac09 100644 (file)
@@ -536,6 +536,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_TEXEL_OFFSET:
                return 7;
 
+       case PIPE_CAP_MAX_VARYINGS:
+               return 32;
+
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
                return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
        case PIPE_CAP_ENDIANNESS:
index bb2d8c09eb102b7cea08490ebad993d21fe703e3..f8ca02d4fcf1c0211c95f742d5109317500c1a86 100644 (file)
@@ -254,6 +254,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
                return 30;
 
+       case PIPE_CAP_MAX_VARYINGS:
+               return 32;
+
        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
                return sscreen->info.chip_class <= VI ?
                        PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
index 44e48cc7ee435cfc6469c71c2046b9dffe799a73..6931b52dc9fcfd3d7ef5ff56d0eb340d52b856b4 100644 (file)
@@ -265,6 +265,8 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 1;
    case PIPE_CAP_CLEAR_TEXTURE:
       return 1;
+   case PIPE_CAP_MAX_VARYINGS:
+      return TGSI_EXEC_MAX_INPUT_ATTRIBS;
    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
index 95dde8b089751b11e0e4724bec35eb8480cabafa..6cb5a14f5b0b5e630b2b92968e1b00deecc916ff 100644 (file)
@@ -350,6 +350,8 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 
    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
       return sws->have_sm4_1 ? 1 : 0; /* only single-channel textures */
+   case PIPE_CAP_MAX_VARYINGS:
+      return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS : 10;
 
    /* Unsupported features */
    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
index bed2c63a64d4d2a3d0af1cf58f9103ac5de26659..c539daf02b943fafb02e52f5afcfc53a6a7869d1 100644 (file)
@@ -177,6 +177,9 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
                 return 4;
 
+        case PIPE_CAP_MAX_VARYINGS:
+                return V3D_MAX_FS_INPUTS / 4;
+
                 /* Texturing. */
         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
index e7f7c82c271c24a8ef02d3e6d9a37b340d3fd863..acb4a1feb0d37adaf223a2f275a97e6189a76216 100644 (file)
@@ -178,6 +178,9 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                 /* Note: Not supported in hardware, just faking it. */
                 return 5;
 
+        case PIPE_CAP_MAX_VARYINGS:
+                return 8;
+
         case PIPE_CAP_VENDOR_ID:
                 return 0x14E4;
         case PIPE_CAP_ACCELERATED:
index 72afd4d95f0b35a04d62173fed9e6e42e47a4e5e..6cc73538a36684d412574f1d13c61d3fab5e0b37 100644 (file)
@@ -260,6 +260,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 1; /* TODO: need to introduce a hw-cap for this */
    case PIPE_CAP_QUERY_BUFFER_OBJECT:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
+   case PIPE_CAP_MAX_VARYINGS:
+      if (vscreen->caps.caps.v1.glsl_level < 150)
+         return vscreen->caps.caps.v2.max_vertex_attribs;
+      return 32;
    case PIPE_CAP_TEXTURE_GATHER_SM5:
    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
    case PIPE_CAP_FAKE_SW_MSAA:
index 8413a8e639c4913cdf18a96bd682426666f670f9..e2b0104ce43d3810416f4d1135812b31375c3651 100644 (file)
@@ -857,6 +857,7 @@ enum pipe_cap
    PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
    PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
    PIPE_CAP_NIR_COMPACT_ARRAYS,
+   PIPE_CAP_MAX_VARYINGS,
 };
 
 /**
index c1a528551cd285f4558e42c9a63bf75b89cb3a7a..2dbda83ca10dca2e723e1a557efa9c6b87f3d8ff 100644 (file)
@@ -365,10 +365,7 @@ void st_init_limits(struct pipe_screen *screen,
    c->Program[MESA_SHADER_VERTEX].MaxAttribs =
       MIN2(c->Program[MESA_SHADER_VERTEX].MaxAttribs, 16);
 
-   /* PIPE_SHADER_CAP_MAX_INPUTS for the FS specifies the maximum number
-    * of inputs. It's always 2 colors + N generic inputs. */
-   c->MaxVarying = screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
-                                            PIPE_SHADER_CAP_MAX_INPUTS);
+   c->MaxVarying = screen->get_param(screen, PIPE_CAP_MAX_VARYINGS);
    c->MaxVarying = MIN2(c->MaxVarying, MAX_VARYING);
    c->MaxGeometryOutputVertices =
       screen->get_param(screen, PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES);