gallium/radeon: remove rcs parameter from radeon_winsys::buffer_set_tiling

This was needed for DRM < 2.12.0 where the kernel was rewriting tiling flags
in IBs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 81929632daf33ee19ff6098bc3149148208082c1..3db7f372c6813dfaf9c873e29c9d169df7c85848 100644 (file)
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1064,7 +1064,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
     tiling.microtile = tex->tex.microtile;
     tiling.macrotile = tex->tex.macrotile[0];
     tiling.stride = tex->tex.stride_in_bytes[0];
-    rws->buffer_set_tiling(tex->buf, NULL, &tiling);
+    rws->buffer_set_tiling(tex->buf, &tiling);
 
     return tex;
 

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index f3087ce3046978cbc0080392e17c7b806d721336..b9f5c61a3c31285a86c4fd985a316ba59042e600 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -253,7 +253,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
        metadata.stride = surface->level[0].pitch_bytes;
        metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
 
-       rscreen->ws->buffer_set_tiling(resource->buf, NULL, &metadata);
+       rscreen->ws->buffer_set_tiling(resource->buf, &metadata);
 
        return rscreen->ws->buffer_get_handle(resource->buf,
                                                surface->level[0].pitch_bytes, whandle);

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 5aaa80d4a1e542c4a1c017b715d83f6178d84f4c..a885df98d5c45fe658c039306bbcafca8549aab3 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -483,11 +483,9 @@ struct radeon_winsys {
      * (tiling info for display code, DRI sharing, and other data)
      *
      * \param buf       A winsys buffer object to set the flags for.
-     * \param cs        A command stream to flush if the buffer is referenced by it.
      * \param md        Metadata
      */
     void (*buffer_set_tiling)(struct pb_buffer *buf,
-                              struct radeon_winsys_cs *rcs,
                               struct radeon_bo_metadata *md);
 
     /**

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 0ed9529a449655dd23d338ebe44b15d563f39c0f..6a79e388311d834d07b84aac51ae9a590b2224be 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -420,7 +420,6 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
 }
 
 static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
-                                 struct radeon_winsys_cs *rcs,
                                 struct radeon_bo_metadata *md)
 {
    struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index ce91af4486fc524c1f7be5dbfede035874693a9f..cd769f7ade90826b709ff0a47d3758be6c24bbaa 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -671,21 +671,13 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
 }
 
 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
-                                 struct radeon_winsys_cs *rcs,
                                 struct radeon_bo_metadata *md)
 {
     struct radeon_bo *bo = radeon_bo(_buf);
-    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
     struct drm_radeon_gem_set_tiling args;
 
     memset(&args, 0, sizeof(args));
 
-    /* Tiling determines how DRM treats the buffer data.
-     * We must flush CS when changing it if the buffer is referenced. */
-    if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
-        cs->flush_cs(cs->flush_data, 0, NULL);
-    }
-
     os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
 
     if (md->microtile == RADEON_LAYOUT_TILED)