adapt LiteSATA to new SoC

diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
index c8f67b3d2ad960da387c2441f35772b44d732265..80452cdfcf977b8d57a4cc26e84e3ceca2802774 100755 (executable)
--- a/misoclib/mem/litesata/example_designs/make.py
+++ b/misoclib/mem/litesata/example_designs/make.py
@@ -69,6 +69,8 @@ if __name__ == "__main__":
        top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
        soc = top_class(platform, **top_kwargs)
        soc.finalize()
+       memory_regions = soc.get_memory_regions()
+       csr_regions = soc.get_csr_regions()
 
        # decode actions
        action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@@ -124,7 +126,7 @@ BIST: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.get_csr_regions())
+               csr_csv = cpuif.get_csr_csv(csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-core"]: