Start expanding on some of the deliverables, with links to documentation and code

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index f187ff095ee44b52f751e5757f1c81c8951604ca..f922f4baa203620f34ed3eb4286b8af934360891 100644 (file)
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -24,11 +24,24 @@ or ASIC for oneself.
 
 See top-level bugreport [#589](https://bugs.libre-soc.org/show_bug.cgi?id=589#c0)
 
-* a set of general-purpose scalar instructions suitable for cryptographic applications
-as well as many other purposes
-* documentation of said instructions (see [[/openpower/sv/bitmanip]] [[/openpower/sv/biginteger]])
-* reference HDL implementation of a number of them
-(not possible within limited 2021-02-051 budget [[nlnet_2021_crypto_router]] )
+**1) A set of general-purpose scalar instructions suitable for cryptographic applications as well as many other purposes**
+
+See [Big integer arithmetic](/openpower/sv/biginteger) and [Bit manipulation](/openpower/sv/bitmanip) for rationale, instruction list and definition in
+pseudo-code.
+
+**2) Implementation and validation of the above instructions on the simulator**
+
+The implementation is scattered within the simulator code, which is available at:
+<https://git.libre-soc.org/?p=openpower-isa.git;a=tree;hb=HEAD>
+
+Unit tests are available at:
+[bigint](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test/bigint;h=38c2ffe30becb7f580053d0aa3a41beca1312567;hb=HEAD) and
+[bitmanip](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/test/bitmanip;h=916950f9e62fd9dac0373b925eaf15199bc7c8ab;hb=HEAD)
+
+**3) Reference HDL implementation of some instructions**
+
+(full implemention was not possible within limited 2021-02-051 budget [[nlnet_2021_crypto_router]])
+
 * additional specification of and simulation for concepts like a REMAP engine and element width
 overrides which, when implemented also in HDL, will allow hyper-efficient acceleration of many
 fundamental crypto algorithms. (implemented 100% in simulator, allowing 100% successful implementation of Simple-V-PowerISA assembler to be made, but limited budget of 2021-02-051 was insufficient to complete HDL implementation of REMAP and elwidths)