radeonsi: don't emit partial flushes for internal CS flushes only

Tested-by: Benedikt Schemmer <ben@besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index 1420702d8d4850f335926b69f80fb62293399f79..d17b2c6a831af0bea93c5efda6e78ab7ddf495a9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -64,10 +64,10 @@ void *si_buffer_map_sync_with_rings(struct si_context *sctx,
            sctx->ws->cs_is_buffer_referenced(sctx->gfx_cs,
                                                resource->buf, rusage)) {
                if (usage & PIPE_TRANSFER_DONTBLOCK) {
-                       si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+                       si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                        return NULL;
                } else {
-                       si_flush_gfx_cs(sctx, 0, NULL);
+                       si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                        busy = true;
                }
        }
@@ -725,7 +725,7 @@ static bool si_resource_commit(struct pipe_context *pctx,
        if (radeon_emitted(ctx->gfx_cs, ctx->initial_gfx_cs_size) &&
            ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs,
                                               res->buf, RADEON_USAGE_READWRITE)) {
-               si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
        }
        if (radeon_emitted(ctx->dma_cs, 0) &&
            ctx->ws->cs_is_buffer_referenced(ctx->dma_cs,

diff --git a/src/gallium/drivers/radeonsi/si_dma_cs.c b/src/gallium/drivers/radeonsi/si_dma_cs.c
index 7af7c5623b7c9345b34abea2eb0b2f857a0de7c4..1eefaeb6ad583cd0d60eb9b74a935affff3f7837 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_dma_cs.c
+++ b/src/gallium/drivers/radeonsi/si_dma_cs.c
@@ -58,7 +58,7 @@ void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
             (src &&
              ctx->ws->cs_is_buffer_referenced(ctx->gfx_cs, src->buf,
                                                 RADEON_USAGE_WRITE))))
-               si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 
        /* Flush if there's not enough space, or if the memory usage per IB
         * is too large.

diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index 26d6c43b34dff1def4a31a322f6125e9ecf4eb26..19fcb96041fcaca37dd6ca4e919d3076fa143c2c 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -374,7 +374,10 @@ static boolean si_fence_finish(struct pipe_screen *screen,
                         * not going to wait.
                         */
                        threaded_context_unwrap_sync(ctx);
-                       si_flush_gfx_cs(sctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
+                       si_flush_gfx_cs(sctx,
+                                       (timeout ? 0 : PIPE_FLUSH_ASYNC) |
+                                        RADEON_FLUSH_START_NEXT_GFX_IB_NOW,
+                                       NULL);
                        rfence->gfx_unflushed.ctx = NULL;
 
                        if (!timeout)

diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 147433b69b67e30e33dab2167f010b1f5f0050ac..ddfdb497364ec5feeb406e87d88ee9f9de79b371 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -47,7 +47,7 @@ void si_need_gfx_cs_space(struct si_context *ctx)
                                                   ctx->vram, ctx->gtt))) {
                ctx->gtt = 0;
                ctx->vram = 0;
-               si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                return;
        }
        ctx->gtt = 0;
@@ -61,7 +61,7 @@ void si_need_gfx_cs_space(struct si_context *ctx)
         */
        unsigned need_dwords = 2048 + ctx->num_cs_dw_queries_suspend;
        if (!ctx->ws->cs_check_space(cs, need_dwords))
-               si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 }
 
 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 125b3a72bfb96670efe5daf3a0a3742e2b1baf02..351c9f4cd3833467e5c165d49f99f1b674666fce 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1340,7 +1340,7 @@ radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
            !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
                                          sctx->vram + rbo->vram_usage,
                                          sctx->gtt + rbo->gart_usage))
-               si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 
        radeon_add_to_buffer_list(sctx, sctx->gfx_cs, rbo, usage, priority);
 }

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 7e1660415f5872fa7ce96de429cc7d50924a90b8..67ab75bbd2d9517c7a3aa0bb33daad25a6b09491 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2774,7 +2774,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 
        /* Flush the context to re-emit both init_config states. */
        sctx->initial_gfx_cs_size = 0; /* force flush */
-       si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+       si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 
        /* Set ring bindings. */
        if (sctx->esgs_ring) {
@@ -3051,7 +3051,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
         */
        si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
        sctx->initial_gfx_cs_size = 0; /* force flush */
-       si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+       si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 }
 
 /**

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 17957f18a5fe995c49ca6c7b3e8fe11fdc16df57..b41a0d1b925ba42746f8b04e9ed242505546c1b0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1869,7 +1869,7 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx,
         * The result is that the kernel memory manager is never a bottleneck.
         */
        if (sctx->num_alloc_tex_transfer_bytes > sctx->screen->info.gart_size / 4) {
-               si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
+               si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                sctx->num_alloc_tex_transfer_bytes = 0;
        }
 

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 22b5a73143d24249c454caebcc907e20aff0d914..9b6d6e83032d079b9d1557182847c1c7f906b185 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -239,7 +239,8 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
              * Only check whether the buffer is being used for write. */
             if (cs && amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
                                                                RADEON_USAGE_WRITE)) {
-               cs->flush_cs(cs->flush_data, PIPE_FLUSH_ASYNC, NULL);
+               cs->flush_cs(cs->flush_data,
+                           RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                return NULL;
             }
 
@@ -249,7 +250,8 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
             }
          } else {
             if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) {
-               cs->flush_cs(cs->flush_data, PIPE_FLUSH_ASYNC, NULL);
+               cs->flush_cs(cs->flush_data,
+                           RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                return NULL;
             }
 
@@ -272,7 +274,8 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
             if (cs) {
                if (amdgpu_bo_is_referenced_by_cs_with_usage(cs, bo,
                                                             RADEON_USAGE_WRITE)) {
-                  cs->flush_cs(cs->flush_data, 0, NULL);
+                  cs->flush_cs(cs->flush_data,
+                              RADEON_FLUSH_START_NEXT_GFX_IB_NOW, NULL);
                } else {
                   /* Try to avoid busy-waiting in amdgpu_bo_wait. */
                   if (p_atomic_read(&bo->num_active_ioctls))
@@ -286,7 +289,8 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
             /* Mapping for write. */
             if (cs) {
                if (amdgpu_bo_is_referenced_by_cs(cs, bo)) {
-                  cs->flush_cs(cs->flush_data, 0, NULL);
+                  cs->flush_cs(cs->flush_data,
+                              RADEON_FLUSH_START_NEXT_GFX_IB_NOW, NULL);
                } else {
                   /* Try to avoid busy-waiting in amdgpu_bo_wait. */
                   if (p_atomic_read(&bo->num_active_ioctls))

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 1617a2fe32e975cde71df467596a14097d912344..6652977e586c37e3026dcad901428c7967beaed1 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -516,7 +516,8 @@ static void *radeon_bo_map(struct pb_buffer *buf,
                  *
                  * Only check whether the buffer is being used for write. */
                 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
-                    cs->flush_cs(cs->flush_data, PIPE_FLUSH_ASYNC, NULL);
+                    cs->flush_cs(cs->flush_data,
+                                RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                     return NULL;
                 }
 
@@ -526,7 +527,8 @@ static void *radeon_bo_map(struct pb_buffer *buf,
                 }
             } else {
                 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
-                    cs->flush_cs(cs->flush_data, PIPE_FLUSH_ASYNC, NULL);
+                    cs->flush_cs(cs->flush_data,
+                                RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
                     return NULL;
                 }
 
@@ -547,7 +549,8 @@ static void *radeon_bo_map(struct pb_buffer *buf,
                  *
                  * Only check whether the buffer is being used for write. */
                 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
-                    cs->flush_cs(cs->flush_data, 0, NULL);
+                    cs->flush_cs(cs->flush_data,
+                                RADEON_FLUSH_START_NEXT_GFX_IB_NOW, NULL);
                 }
                 radeon_bo_wait((struct pb_buffer*)bo, PIPE_TIMEOUT_INFINITE,
                                RADEON_USAGE_WRITE);
@@ -555,7 +558,8 @@ static void *radeon_bo_map(struct pb_buffer *buf,
                 /* Mapping for write. */
                 if (cs) {
                     if (radeon_bo_is_referenced_by_cs(cs, bo)) {
-                        cs->flush_cs(cs->flush_data, 0, NULL);
+                        cs->flush_cs(cs->flush_data,
+                                    RADEON_FLUSH_START_NEXT_GFX_IB_NOW, NULL);
                     } else {
                         /* Try to avoid busy-waiting in radeon_bo_wait. */
                         if (p_atomic_read(&bo->num_active_ioctls))

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index a1975dff8df64cf9e3cf44f02aa70f246eb40593..9070464bec8347a31a606faac9c7c5cfe126317d 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -407,7 +407,8 @@ static bool radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
 
         /* Flush if there are any relocs. Clean up otherwise. */
         if (cs->csc->num_relocs) {
-            cs->flush_cs(cs->flush_data, PIPE_FLUSH_ASYNC, NULL);
+            cs->flush_cs(cs->flush_data,
+                        RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
         } else {
             radeon_cs_context_cleanup(cs->csc);
             cs->base.used_vram = 0;