aarch64: Add +sme2
authorRichard Sandiford <richard.sandiford@arm.com>
Thu, 30 Mar 2023 10:09:10 +0000 (11:09 +0100)
committerRichard Sandiford <richard.sandiford@arm.com>
Thu, 30 Mar 2023 10:09:10 +0000 (11:09 +0100)
This patch adds bare-bones support for +sme2.  Later patches
fill in the rest.

gas/NEWS
gas/config/tc-aarch64.c
gas/doc/c-aarch64.texi
include/opcode/aarch64.h

index 4ae2089901c89e84293e1e5bf42c7cbedf372abf..05fbed113c27f7904597d2f589ea6f4e2c4069df 100644 (file)
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add SME2 support to the AArch64 port.
+
 Changes in 2.40:
 
 * Add support for Intel RAO-INT instructions.
index 2d4c6106506611d84562bb8e4f97403529bbdacd..6ebfcda7dff54d31f4af1653fa9d7793bac24409 100644 (file)
@@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
                        AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
   {"sme-i16i64",       AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
+  {"sme2",             AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
   {"bf16",             AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
   {"i8mm",             AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
index 3921c0d368e866ec9a51d65a470fb15a0eff5fbb..acde4a77dd25f20398c41222ce66bbc64cc99bbd 100644 (file)
@@ -235,6 +235,8 @@ automatically cause those extensions to be disabled.
  @tab Enable SME F64F64 Extension.
 @item @code{sme-i16i64} @tab Armv9-A @tab No
  @tab Enable SME I16I64 Extension.
+@item @code{sme2} @tab Armv9-A @tab No
+ @tab Enable SME2.  This implies @code{sme}.
 @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
  @tab Enable Speculative Store Bypassing Safe state read and write.
 @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
index ef59d531d176621ed351db9fdcb0e8d971e383fc..5c9b5e5dac10da2b4511204ea23ec576b3d01ab4 100644 (file)
@@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SME_I16I64   (1ULL << 58) /* SME I16I64.  */
 #define AARCH64_FEATURE_V8_8        (1ULL << 59) /* Armv8.8 processors.  */
 #define AARCH64_FEATURE_CSSC        (1ULL << 60) /* Common Short Sequence Compression instructions.  */
+#define AARCH64_FEATURE_SME2        (1ULL << 61) /* SME2.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)