don't depend on the memory system to return the atomic cpu a multiple of cpu cycles.

--HG--
extra : convert_revision : e5eb36f14c8394381a0269fefd34a178833c8346

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 071193f02e01a4154c658ba91b9d81be6ada515a..ce28ba9c8ddff00fe6e41e7d3d35440e24b60689 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -410,15 +410,14 @@ AtomicSimpleCPU::tick()
             postExecute();
 
             if (simulate_stalls) {
-                // This calculation assumes that the icache and dcache
-                // access latencies are always a multiple of the CPU's
-                // cycle time.  If not, the next tick event may get
-                // scheduled at a non-integer multiple of the CPU
-                // cycle time.
                 Tick icache_stall = icache_latency - cycles(1);
                 Tick dcache_stall =
                     dcache_access ? dcache_latency - cycles(1) : 0;
-                latency += icache_stall + dcache_stall;
+                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
+                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
+                    latency += cycles(stall_cycles+1);
+                else
+                    latency += cycles(stall_cycles);
             }
 
         }