bugfix in blif front-end

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 4b4ac609869e697b03b851082f908ab8409eb1fe..580fb8647d76bd9f69aacb27648b28bf05af47ee 100644 (file)
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -207,10 +207,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name)
                                RTLIL::SigSpec input_sig, output_sig;
                                while ((p = strtok(NULL, " \t\r\n")) != NULL) {
                                        RTLIL::Wire *wire;
-                                       if (module->wires_.count(stringf("\\%s", p)) > 0) {
-                                               wire = module->wires_.at(stringf("\\%s", p));
+                                       if (module->wires_.count(RTLIL::escape_id(p)) > 0) {
+                                               wire = module->wires_.at(RTLIL::escape_id(p));
                                        } else {
-                                               wire = module->addWire(stringf("\\%s", p));
+                                               wire = module->addWire(RTLIL::escape_id(p));
                                        }
                                        input_sig.append(wire);
                                }

diff --git a/tests/vloghtb/test_febe.sh b/tests/vloghtb/test_febe.sh
index 7756202c470133674122d8b78d1e106bd903c4d0..482d44d9aa21f3c5f7f46a9c41c79e388e40e259 100644 (file)
--- a/tests/vloghtb/test_febe.sh
+++ b/tests/vloghtb/test_febe.sh
@@ -6,8 +6,8 @@ source common.sh
 f=$1
 n=$(basename ${f%.v})
 
-test_febe vlog1 "synth"                   ".v"    "write_verilog"      "read_verilog"         "-ignore_div_by_zero" $n $f
-test_febe vlog2 "synth -run coarse"       ".v"    "write_verilog"      "read_verilog -icells" "-ignore_div_by_zero" $n $f
-test_febe blif  "synth; splitnets -ports" ".blif" "write_blif -icells" "read_blif"            "-ignore_div_by_zero" $n $f
+test_febe vlog1 "synth"                   ".v"    "write_verilog" "read_verilog"         "-ignore_div_by_zero" $n $f
+test_febe vlog2 "synth -run coarse"       ".v"    "write_verilog" "read_verilog -icells" "-ignore_div_by_zero" $n $f
+test_febe blif  "synth; splitnets -ports" ".blif" "write_blif"    "read_blif"            "-ignore_div_by_zero" $n $f
 
 exit 0