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broadcom/vc5: Drop alignment bits from Z/S rendering mode config address.
authorEric Anholt <eric@anholt.net>
Wed, 25 Oct 2017 02:13:17 +0000 (19:13 -0700)
committerEric Anholt <eric@anholt.net>
Mon, 30 Oct 2017 20:31:16 +0000 (13:31 -0700)
Improves CLIF dumping output.

src/broadcom/cle/v3d_packet_v33.xml patch | blob | history

diff --git a/src/broadcom/cle/v3d_packet_v33.xml b/src/broadcom/cle/v3d_packet_v33.xml
index 86fc81021459721f7207d0f79c413b8614ea9086..3be33f41a08195199a62768a5f814b3a3aad2435 100644 (file)
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -528,7 +528,7 @@
   </packet>
 
   <packet code="121" name="Tile Rendering Mode Configuration (Z/Stencil config)" cl="R">
-    <field name="Address" size="32" start="32" type="address"/>
+    <field name="Address" size="26" start="38" type="address"/>
 
     <field name="Padded height of output image in UIF blocks" size="13" start="25" type="uint"/>