radv: prepare fmask surface creation

The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.

This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.

v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
  apply this patch separately *before* switching to ac_compute_surface
  and hopefully avoid intermittent regressions (Nicolai)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 63cbc6bf92452b41c35fa28130afdc05e193846d..2065545f20dc4b96309d155ed4ea911269fac50e 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -459,22 +459,21 @@ radv_image_get_fmask_info(struct radv_device *device,
                          struct radv_fmask_info *out)
 {
        /* FMASK is allocated like an ordinary texture. */
-       struct radeon_surf fmask = image->surface;
+       struct radeon_surf fmask = {};
        struct ac_surf_info info = image->info;
        memset(out, 0, sizeof(*out));
 
-       fmask.surf_alignment = 0;
-       fmask.surf_size = 0;
-       fmask.flags |= RADEON_SURF_FMASK;
+       fmask.blk_w = image->surface.blk_w;
+       fmask.blk_h = image->surface.blk_h;
        info.samples = 1;
+       fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
+
        /* Force 2D tiling if it wasn't set. This may occur when creating
         * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
         * destination buffer must have an FMASK too. */
        fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
        fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
 
-       fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-
        switch (nr_samples) {
        case 2:
        case 4:

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index 508a6d1f733a0d47fa2af94787bcb03b1365e945..4ba9e0cdf9bf5af787ab914e5a77dfd63bc1a3a5 100644 (file)
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -322,10 +322,11 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
 
        AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
        AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
+       AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
        AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
        AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
        AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
-       AddrSurfInfoIn.flags.opt4Space = 1;
+       AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.fmask;
 
        /* DCC notes:
         * - If we add MSAA support, keep in mind that CB can't decompress 8bpp