i386.md (*movsf_internal): AVX falsedep fix.

2018-05-21  Alexander Nesterovskiy  <alexander.nesterovskiy@intel.com>

gcc/
        * config/i386/i386.md (*movsf_internal): AVX falsedep fix.
        (*movdf_internal): Ditto.
        (*rcpsf2_sse): Ditto.
        (*rsqrtsf2_sse): Ditto.
        (*sqrt<mode>2_sse): Ditto.

From-SVN: r260436

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 27b5c60af169531f4891f30c79570b1a2101422b..b1a9017d0c15b29849cc3f227d1159bc15ed60e2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2018-05-21  Alexander Nesterovskiy  <alexander.nesterovskiy@intel.com>
+
+       * config/i386/i386.md (*movsf_internal): AVX falsedep fix.
+       (*movdf_internal): Ditto.
+       (*rcpsf2_sse): Ditto.
+       (*rsqrtsf2_sse): Ditto.
+       (*sqrt<mode>2_sse): Ditto.
+
 2018-05-21  Tamar Christina  <tamar.christina@arm.com>
 
        * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 706b7f59be04b3d2d931b7ae2c8173d1cd9bee16..cc993b3aad8f806142d5da48a6e775f8e2e49a4b 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3559,7 +3559,7 @@
        {
        case MODE_DF:
          if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
-           return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
+           return "vmovsd\t{%d1, %0|%0, %d1}";
          return "%vmovsd\t{%1, %0|%0, %1}";
 
        case MODE_V4SF:
@@ -3760,7 +3760,7 @@
        {
        case MODE_SF:
          if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
-           return "vmovss\t{%1, %0, %0|%0, %0, %1}";
+           return "vmovss\t{%d1, %0|%0, %d1}";
          return "%vmovss\t{%1, %0|%0, %1}";
 
        case MODE_V16SF:
@@ -15126,11 +15126,13 @@
         (symbol_ref "false"))))])
 
 (define_insn "*rcpsf2_sse"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+  [(set (match_operand:SF 0 "register_operand" "=x,x")
+       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
                   UNSPEC_RCP))]
   "TARGET_SSE && TARGET_SSE_MATH"
-  "%vrcpss\t{%1, %d0|%d0, %1}"
+  "@
+   %vrcpss\t{%d1, %0|%0, %d1}
+   %vrcpss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
@@ -15428,11 +15430,13 @@
    (set_attr "bdver1_decode" "direct")])
 
 (define_insn "*rsqrtsf2_sse"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+  [(set (match_operand:SF 0 "register_operand" "=x,x")
+       (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
                   UNSPEC_RSQRT))]
   "TARGET_SSE && TARGET_SSE_MATH"
-  "%vrsqrtss\t{%1, %d0|%d0, %1}"
+  "@
+   %vrsqrtss\t{%d1, %0|%0, %d1}
+   %vrsqrtss\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "rcp")
    (set_attr "btver2_sse_attr" "rcp")
@@ -15450,11 +15454,13 @@
 })
 
 (define_insn "*sqrt<mode>2_sse"
-  [(set (match_operand:MODEF 0 "register_operand" "=v")
+  [(set (match_operand:MODEF 0 "register_operand" "=v,v")
        (sqrt:MODEF
-         (match_operand:MODEF 1 "nonimmediate_operand" "vm")))]
+         (match_operand:MODEF 1 "nonimmediate_operand" "v,m")))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
-  "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
+  "@
+   %vsqrt<ssemodesuffix>\t{%d1, %0|%0, %d1}
+   %vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "sqrt")
    (set_attr "btver2_sse_attr" "sqrt")