+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.slave[2]
-icache_port=system.membus.slave[1]
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "membus": {
- "point_of_coherency": true,
- "system": "system",
- "response_latency": 2,
- "cxx_class": "CoherentXBar",
- "forward_latency": 4,
- "clk_domain": "system.clk_domain",
- "width": 16,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 3,
- "slave": {
- "peer": [
- "system.system_port",
- "system.cpu.icache_port",
- "system.cpu.dcache_port"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": null,
- "power_model": null,
- "path": "system.membus",
- "snoop_response_latency": 4,
- "name": "membus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "symbolfile": "",
- "readfile": "",
- "thermal_model": null,
- "cxx_class": "System",
- "work_begin_cpu_id_exit": -1,
- "load_offset": 0,
- "work_begin_exit_count": 0,
- "p_state_clk_gate_min": 1000,
- "memories": [
- "system.physmem"
- ],
- "work_begin_ckpt_count": 0,
- "clk_domain": {
- "name": "clk_domain",
- "clock": [
- 1000
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "mem_ranges": [],
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "dvfs_handler": {
- "enable": false,
- "name": "dvfs_handler",
- "sys_clk_domain": "system.clk_domain",
- "transition_latency": 100000000,
- "eventq_index": 0,
- "cxx_class": "DVFSHandler",
- "domains": [],
- "path": "system.dvfs_handler",
- "type": "DVFSHandler"
- },
- "work_end_exit_count": 0,
- "type": "System",
- "voltage_domain": {
- "name": "voltage_domain",
- "eventq_index": 0,
- "voltage": [
- "1.0"
- ],
- "cxx_class": "VoltageDomain",
- "path": "system.voltage_domain",
- "type": "VoltageDomain"
- },
- "cache_line_size": 64,
- "boot_osflags": "a",
- "system_port": {
- "peer": "system.membus.slave[0]",
- "role": "MASTER"
- },
- "physmem": {
- "range": "0:134217727",
- "latency": 30000,
- "name": "physmem",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "latency_var": 0,
- "bandwidth": "73.000000",
- "conf_table_reported": true,
- "cxx_class": "SimpleMemory",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.physmem",
- "null": false,
- "type": "SimpleMemory",
- "port": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "in_addr_map": true
- },
- "power_model": null,
- "work_cpus_ckpt_count": 0,
- "thermal_components": [],
- "path": "system",
- "cpu_clk_domain": {
- "name": "cpu_clk_domain",
- "clock": [
- 500
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.cpu_clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "work_end_ckpt_count": 0,
- "mem_mode": "atomic",
- "name": "system",
- "init_param": 0,
- "p_state_clk_gate_bins": 20,
- "load_addr_mask": 1099511627775,
- "cpu": [
- {
- "do_statistics_insts": true,
- "numThreads": 1,
- "itb": {
- "name": "itb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu.itb",
- "type": "AlphaTLB",
- "size": 48
- },
- "simulate_data_stalls": false,
- "function_trace": false,
- "do_checkpoint_insts": true,
- "cxx_class": "AtomicSimpleCPU",
- "max_loads_all_threads": 0,
- "system": "system",
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "cpu_id": 0,
- "width": 1,
- "checker": null,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "do_quiesce": true,
- "type": "AtomicSimpleCPU",
- "fastmem": false,
- "profile": 0,
- "icache_port": {
- "peer": "system.membus.slave[1]",
- "role": "MASTER"
- },
- "p_state_clk_gate_bins": 20,
- "p_state_clk_gate_min": 1000,
- "interrupts": [
- {
- "eventq_index": 0,
- "path": "system.cpu.interrupts",
- "type": "AlphaInterrupts",
- "name": "interrupts",
- "cxx_class": "AlphaISA::Interrupts"
- }
- ],
- "dcache_port": {
- "peer": "system.membus.slave[2]",
- "role": "MASTER"
- },
- "socket_id": 0,
- "power_model": null,
- "max_insts_all_threads": 0,
- "path": "system.cpu",
- "max_loads_any_thread": 0,
- "switched_out": false,
- "workload": [
- {
- "name": "workload",
- "output": "cout",
- "chkpt": "",
- "errout": "cerr",
- "kvmInSE": false,
- "system": "system",
- "useArchPT": false,
- "eventq_index": 0,
- "file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
- "cxx_class": "EioProcess",
- "path": "system.cpu.workload",
- "max_stack_size": 67108864,
- "type": "EioProcess",
- "input": "cin"
- }
- ],
- "name": "cpu",
- "dtb": {
- "name": "dtb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu.dtb",
- "type": "AlphaTLB",
- "size": 64
- },
- "simpoint_start_insts": [],
- "max_insts_any_thread": 500000,
- "simulate_inst_stalls": false,
- "progress_interval": 0,
- "branchPred": null,
- "isa": [
- {
- "name": "isa",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- }
- ],
- "multi_thread": false,
- "exit_on_work_items": false,
- "work_item_id": -1,
- "num_work_ids": 16
- },
- "time_sync_period": 100000000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 100000000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": false
-}
\ No newline at end of file
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout: Broken pipe
+++ /dev/null
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jun 12 2016 19:14:13
-gem5 started Jun 12 2016 19:14:37
-gem5 executing on zizzer, pid 29746
-command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-atomic
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 250015500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1177687 # Simulator instruction rate (inst/s)
-host_op_rate 1177628 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 588821738 # Simulator tick rate (ticks/s)
-host_mem_usage 224108 # Number of bytes of host memory used
-host_seconds 0.42 # Real time elapsed on the host
-sim_insts 500001 # Number of instructions simulated
-sim_ops 500001 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory
-system.physmem.bytes_written::total 417562 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.data_hits 180775 # DTB hits
-system.cpu.dtb.data_misses 18 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 180793 # DTB accesses
-system.cpu.itb.fetch_hits 500019 # ITB hits
-system.cpu.itb.fetch_misses 13 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 500032 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 500032 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 500001 # Number of instructions committed
-system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu.num_func_calls 14357 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu.num_int_insts 474689 # number of integer instructions
-system.cpu.num_fp_insts 32 # number of float instructions
-system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 180793 # number of memory refs
-system.cpu.num_load_insts 124443 # Number of load instructions
-system.cpu.num_store_insts 56350 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 500032 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 59023 # Number of branches fetched
-system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 500019 # Class of executed instruction
-system.membus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 624454 # Transaction distribution
-system.membus.trans_dist::ReadResp 624454 # Transaction distribution
-system.membus.trans_dist::WriteReq 56340 # Transaction distribution
-system.membus.trans_dist::WriteResp 56340 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 680794 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram
-system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 680794 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu.l2cache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=2097152
-system=system
-tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=2097152
-
-[system.cpu.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.cpu.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
-[system.cpu.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.cpu.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.membus]
-type=CoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "membus": {
- "point_of_coherency": true,
- "system": "system",
- "response_latency": 2,
- "cxx_class": "CoherentXBar",
- "forward_latency": 4,
- "clk_domain": "system.clk_domain",
- "width": 16,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 3,
- "slave": {
- "peer": [
- "system.system_port",
- "system.cpu.l2cache.mem_side"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": null,
- "power_model": null,
- "path": "system.membus",
- "snoop_response_latency": 4,
- "name": "membus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "symbolfile": "",
- "readfile": "",
- "thermal_model": null,
- "cxx_class": "System",
- "work_begin_cpu_id_exit": -1,
- "load_offset": 0,
- "work_begin_exit_count": 0,
- "p_state_clk_gate_min": 1000,
- "memories": [
- "system.physmem"
- ],
- "work_begin_ckpt_count": 0,
- "clk_domain": {
- "name": "clk_domain",
- "clock": [
- 1000
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "mem_ranges": [],
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "dvfs_handler": {
- "enable": false,
- "name": "dvfs_handler",
- "sys_clk_domain": "system.clk_domain",
- "transition_latency": 100000000,
- "eventq_index": 0,
- "cxx_class": "DVFSHandler",
- "domains": [],
- "path": "system.dvfs_handler",
- "type": "DVFSHandler"
- },
- "work_end_exit_count": 0,
- "type": "System",
- "voltage_domain": {
- "name": "voltage_domain",
- "eventq_index": 0,
- "voltage": [
- "1.0"
- ],
- "cxx_class": "VoltageDomain",
- "path": "system.voltage_domain",
- "type": "VoltageDomain"
- },
- "cache_line_size": 64,
- "boot_osflags": "a",
- "system_port": {
- "peer": "system.membus.slave[0]",
- "role": "MASTER"
- },
- "physmem": {
- "range": "0:134217727",
- "latency": 30000,
- "name": "physmem",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "latency_var": 0,
- "bandwidth": "73.000000",
- "conf_table_reported": true,
- "cxx_class": "SimpleMemory",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.physmem",
- "null": false,
- "type": "SimpleMemory",
- "port": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "in_addr_map": true
- },
- "power_model": null,
- "work_cpus_ckpt_count": 0,
- "thermal_components": [],
- "path": "system",
- "cpu_clk_domain": {
- "name": "cpu_clk_domain",
- "clock": [
- 500
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.cpu_clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "work_end_ckpt_count": 0,
- "mem_mode": "timing",
- "name": "system",
- "init_param": 0,
- "p_state_clk_gate_bins": 20,
- "load_addr_mask": 1099511627775,
- "cpu": [
- {
- "do_statistics_insts": true,
- "numThreads": 1,
- "itb": {
- "name": "itb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu.itb",
- "type": "AlphaTLB",
- "size": 48
- },
- "system": "system",
- "icache": {
- "cpu_side": {
- "peer": "system.cpu.icache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 131072,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 2,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu.icache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 131072
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.cpu.toL2Bus.slave[0]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": true,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": true,
- "prefetch_on_access": false,
- "path": "system.cpu.icache",
- "mshrs": 4,
- "name": "icache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 2
- },
- "function_trace": false,
- "do_checkpoint_insts": true,
- "cxx_class": "TimingSimpleCPU",
- "max_loads_all_threads": 0,
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "cpu_id": 0,
- "checker": null,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "toL2Bus": {
- "point_of_coherency": false,
- "system": "system",
- "response_latency": 1,
- "cxx_class": "CoherentXBar",
- "forward_latency": 0,
- "clk_domain": "system.cpu_clk_domain",
- "width": 32,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.cpu.l2cache.cpu_side"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 1,
- "slave": {
- "peer": [
- "system.cpu.icache.mem_side",
- "system.cpu.dcache.mem_side"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": {
- "name": "snoop_filter",
- "system": "system",
- "max_capacity": 8388608,
- "eventq_index": 0,
- "cxx_class": "SnoopFilter",
- "path": "system.cpu.toL2Bus.snoop_filter",
- "type": "SnoopFilter",
- "lookup_latency": 0
- },
- "power_model": null,
- "path": "system.cpu.toL2Bus",
- "snoop_response_latency": 1,
- "name": "toL2Bus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "do_quiesce": true,
- "type": "TimingSimpleCPU",
- "profile": 0,
- "icache_port": {
- "peer": "system.cpu.icache.cpu_side",
- "role": "MASTER"
- },
- "p_state_clk_gate_bins": 20,
- "p_state_clk_gate_min": 1000,
- "interrupts": [
- {
- "eventq_index": 0,
- "path": "system.cpu.interrupts",
- "type": "AlphaInterrupts",
- "name": "interrupts",
- "cxx_class": "AlphaISA::Interrupts"
- }
- ],
- "dcache_port": {
- "peer": "system.cpu.dcache.cpu_side",
- "role": "MASTER"
- },
- "socket_id": 0,
- "power_model": null,
- "max_insts_all_threads": 0,
- "l2cache": {
- "cpu_side": {
- "peer": "system.cpu.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 20,
- "cxx_class": "Cache",
- "size": 2097152,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu.l2cache.tags",
- "hit_latency": 20,
- "block_size": 64,
- "type": "LRU",
- "size": 2097152
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.membus.slave[1]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 20,
- "tgts_per_mshr": 12,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.cpu.l2cache",
- "mshrs": 20,
- "name": "l2cache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 8
- },
- "path": "system.cpu",
- "max_loads_any_thread": 0,
- "switched_out": false,
- "workload": [
- {
- "name": "workload",
- "output": "cout",
- "chkpt": "",
- "errout": "cerr",
- "kvmInSE": false,
- "system": "system",
- "useArchPT": false,
- "eventq_index": 0,
- "file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
- "cxx_class": "EioProcess",
- "path": "system.cpu.workload",
- "max_stack_size": 67108864,
- "type": "EioProcess",
- "input": "cin"
- }
- ],
- "name": "cpu",
- "dtb": {
- "name": "dtb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu.dtb",
- "type": "AlphaTLB",
- "size": 64
- },
- "simpoint_start_insts": [],
- "max_insts_any_thread": 500000,
- "progress_interval": 0,
- "branchPred": null,
- "dcache": {
- "cpu_side": {
- "peer": "system.cpu.dcache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 262144,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 2,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu.dcache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 262144
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.cpu.toL2Bus.slave[1]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.cpu.dcache",
- "mshrs": 4,
- "name": "dcache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 2
- },
- "isa": [
- {
- "name": "isa",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- }
- ],
- "multi_thread": false,
- "exit_on_work_items": false,
- "work_item_id": -1,
- "num_work_ids": 16
- },
- "time_sync_period": 100000000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 100000000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": false
-}
\ No newline at end of file
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout: Broken pipe
+++ /dev/null
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jun 12 2016 19:14:13
-gem5 started Jun 12 2016 19:14:35
-gem5 executing on zizzer, pid 29706
-command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/20.eio-short/alpha/eio/simple-timing
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-49508 bytes wasted
->Exiting @ tick 733071500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000733 # Number of seconds simulated
-sim_ticks 733071500 # Number of ticks simulated
-final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 714823 # Simulator instruction rate (inst/s)
-host_op_rate 714800 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1047966347 # Simulator tick rate (ticks/s)
-host_mem_usage 233664 # Number of bytes of host memory used
-host_seconds 0.70 # Real time elapsed on the host
-sim_insts 500001 # Number of instructions simulated
-sim_ops 500001 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 54848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 124435 # DTB read hits
-system.cpu.dtb.read_misses 8 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 124443 # DTB read accesses
-system.cpu.dtb.write_hits 56340 # DTB write hits
-system.cpu.dtb.write_misses 10 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 56350 # DTB write accesses
-system.cpu.dtb.data_hits 180775 # DTB hits
-system.cpu.dtb.data_misses 18 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 180793 # DTB accesses
-system.cpu.itb.fetch_hits 500020 # ITB hits
-system.cpu.itb.fetch_misses 13 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 500033 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 733071500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1466143 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 500001 # Number of instructions committed
-system.cpu.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu.num_func_calls 14357 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu.num_int_insts 474689 # number of integer instructions
-system.cpu.num_fp_insts 32 # number of float instructions
-system.cpu.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_mem_refs 180793 # number of memory refs
-system.cpu.num_load_insts 124443 # Number of load instructions
-system.cpu.num_store_insts 56350 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 1466143 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 59023 # Number of branches fetched
-system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 500019 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits
-system.cpu.dcache.overall_hits::total 180321 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
-system.cpu.dcache.overall_misses::total 454 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 19215000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8479000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8479000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27694000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 27694000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27694000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 27694000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002531 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002511 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002511 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22473000 # number of overall MSHR miss cycles
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-system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution
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-system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram
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-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 733071500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 718 # Transaction distribution
-system.membus.trans_dist::ReadExReq 139 # Transaction distribution
-system.membus.trans_dist::ReadExResp 139 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 857 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 857 # Request fanout histogram
-system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-
-require_sim_object("EioProcess")
-
-root.system.cpu[0].workload = EioProcess(file = binpath('anagram',
- 'anagram-vshort.eio.gz'))
-root.system.cpu[0].max_insts_any_thread = 500000
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=atomic
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu0.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=system.cpu1.workload
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu1.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu2]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=2
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu2.interrupts
-isa=system.cpu2.isa
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu2.tracer
-width=1
-workload=system.cpu2.workload
-dcache_port=system.cpu2.dcache.cpu_side
-icache_port=system.cpu2.icache.cpu_side
-
-[system.cpu2.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.slave[5]
-
-[system.cpu2.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu2.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.slave[4]
-
-[system.cpu2.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu2.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu2.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu2.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu2.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu3]
-type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=3
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu3.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu3.interrupts
-isa=system.cpu3.isa
-itb=system.cpu3.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu3.tracer
-width=1
-workload=system.cpu3.workload
-dcache_port=system.cpu3.dcache.cpu_side
-icache_port=system.cpu3.icache.cpu_side
-
-[system.cpu3.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.slave[7]
-
-[system.cpu3.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu3.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.slave[6]
-
-[system.cpu3.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu3.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu3.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu3.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu3.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.l2c.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "membus": {
- "point_of_coherency": true,
- "system": "system",
- "response_latency": 2,
- "cxx_class": "CoherentXBar",
- "forward_latency": 4,
- "clk_domain": "system.clk_domain",
- "width": 16,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 3,
- "slave": {
- "peer": [
- "system.system_port",
- "system.l2c.mem_side"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": {
- "name": "snoop_filter",
- "system": "system",
- "max_capacity": 8388608,
- "eventq_index": 0,
- "cxx_class": "SnoopFilter",
- "path": "system.membus.snoop_filter",
- "type": "SnoopFilter",
- "lookup_latency": 1
- },
- "power_model": null,
- "path": "system.membus",
- "snoop_response_latency": 4,
- "name": "membus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "symbolfile": "",
- "l2c": {
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 20,
- "cxx_class": "Cache",
- "size": 4194304,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.l2c.tags",
- "hit_latency": 20,
- "block_size": 64,
- "type": "LRU",
- "size": 4194304
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.membus.slave[1]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 20,
- "tgts_per_mshr": 12,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.l2c",
- "mshrs": 20,
- "name": "l2c",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 8
- },
- "readfile": "",
- "thermal_model": null,
- "cxx_class": "System",
- "work_begin_cpu_id_exit": -1,
- "load_offset": 0,
- "work_begin_exit_count": 0,
- "p_state_clk_gate_min": 1000,
- "memories": [
- "system.physmem"
- ],
- "work_begin_ckpt_count": 0,
- "clk_domain": {
- "name": "clk_domain",
- "clock": [
- 1000
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "mem_ranges": [],
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "dvfs_handler": {
- "enable": false,
- "name": "dvfs_handler",
- "sys_clk_domain": "system.clk_domain",
- "transition_latency": 100000000,
- "eventq_index": 0,
- "cxx_class": "DVFSHandler",
- "domains": [],
- "path": "system.dvfs_handler",
- "type": "DVFSHandler"
- },
- "work_end_exit_count": 0,
- "type": "System",
- "voltage_domain": {
- "name": "voltage_domain",
- "eventq_index": 0,
- "voltage": [
- "1.0"
- ],
- "cxx_class": "VoltageDomain",
- "path": "system.voltage_domain",
- "type": "VoltageDomain"
- },
- "cache_line_size": 64,
- "boot_osflags": "a",
- "system_port": {
- "peer": "system.membus.slave[0]",
- "role": "MASTER"
- },
- "physmem": {
- "range": "0:134217727",
- "latency": 30000,
- "name": "physmem",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.clk_domain",
- "power_model": null,
- "latency_var": 0,
- "bandwidth": "73.000000",
- "conf_table_reported": true,
- "cxx_class": "SimpleMemory",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.physmem",
- "null": false,
- "type": "SimpleMemory",
- "port": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "in_addr_map": true
- },
- "power_model": null,
- "work_cpus_ckpt_count": 0,
- "thermal_components": [],
- "path": "system",
- "cpu_clk_domain": {
- "name": "cpu_clk_domain",
- "clock": [
- 500
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.cpu_clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "toL2Bus": {
- "point_of_coherency": false,
- "system": "system",
- "response_latency": 1,
- "cxx_class": "CoherentXBar",
- "forward_latency": 0,
- "clk_domain": "system.cpu_clk_domain",
- "width": 32,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.l2c.cpu_side"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 1,
- "slave": {
- "peer": [
- "system.cpu0.icache.mem_side",
- "system.cpu0.dcache.mem_side",
- "system.cpu1.icache.mem_side",
- "system.cpu1.dcache.mem_side",
- "system.cpu2.icache.mem_side",
- "system.cpu2.dcache.mem_side",
- "system.cpu3.icache.mem_side",
- "system.cpu3.dcache.mem_side"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": {
- "name": "snoop_filter",
- "system": "system",
- "max_capacity": 8388608,
- "eventq_index": 0,
- "cxx_class": "SnoopFilter",
- "path": "system.toL2Bus.snoop_filter",
- "type": "SnoopFilter",
- "lookup_latency": 0
- },
- "power_model": null,
- "path": "system.toL2Bus",
- "snoop_response_latency": 1,
- "name": "toL2Bus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "work_end_ckpt_count": 0,
- "mem_mode": "atomic",
- "name": "system",
- "init_param": 0,
- "p_state_clk_gate_bins": 20,
- "load_addr_mask": 1099511627775,
- "cpu": [
- {
- "do_statistics_insts": true,
- "numThreads": 1,
- "itb": {
- "name": "itb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu0.itb",
- "type": "AlphaTLB",
- "size": 48
- },
- "simulate_data_stalls": false,
- "icache": {
- "cpu_side": {
- "peer": "system.cpu0.icache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 32768,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 1,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu0.icache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 32768
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[0]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": true,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": true,
- "prefetch_on_access": false,
- "path": "system.cpu0.icache",
- "mshrs": 4,
- "name": "icache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 1
- },
- "function_trace": false,
- "do_checkpoint_insts": true,
- "cxx_class": "AtomicSimpleCPU",
- "max_loads_all_threads": 0,
- "system": "system",
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "cpu_id": 0,
- "width": 1,
- "checker": null,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "do_quiesce": true,
- "type": "AtomicSimpleCPU",
- "fastmem": false,
- "profile": 0,
- "icache_port": {
- "peer": "system.cpu0.icache.cpu_side",
- "role": "MASTER"
- },
- "p_state_clk_gate_bins": 20,
- "p_state_clk_gate_min": 1000,
- "interrupts": [
- {
- "eventq_index": 0,
- "path": "system.cpu0.interrupts",
- "type": "AlphaInterrupts",
- "name": "interrupts",
- "cxx_class": "AlphaISA::Interrupts"
- }
- ],
- "dcache_port": {
- "peer": "system.cpu0.dcache.cpu_side",
- "role": "MASTER"
- },
- "socket_id": 0,
- "power_model": null,
- "max_insts_all_threads": 0,
- "path": "system.cpu0",
- "max_loads_any_thread": 0,
- "switched_out": false,
- "workload": [
- {
- "name": "workload",
- "output": "cout",
- "chkpt": "",
- "errout": "cerr",
- "kvmInSE": false,
- "system": "system",
- "useArchPT": false,
- "eventq_index": 0,
- "file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
- "cxx_class": "EioProcess",
- "path": "system.cpu0.workload",
- "max_stack_size": 67108864,
- "type": "EioProcess",
- "input": "cin"
- }
- ],
- "name": "cpu0",
- "dtb": {
- "name": "dtb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu0.dtb",
- "type": "AlphaTLB",
- "size": 64
- },
- "simpoint_start_insts": [],
- "max_insts_any_thread": 500000,
- "simulate_inst_stalls": false,
- "progress_interval": 0,
- "branchPred": null,
- "dcache": {
- "cpu_side": {
- "peer": "system.cpu0.dcache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 32768,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 4,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu0.dcache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 32768
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[1]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.cpu0.dcache",
- "mshrs": 4,
- "name": "dcache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 4
- },
- "isa": [
- {
- "name": "isa",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu0.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu0.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- },
- {
- "do_statistics_insts": true,
- "numThreads": 1,
- "itb": {
- "name": "itb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu1.itb",
- "type": "AlphaTLB",
- "size": 48
- },
- "simulate_data_stalls": false,
- "icache": {
- "cpu_side": {
- "peer": "system.cpu1.icache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 32768,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 1,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu1.icache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 32768
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[2]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": true,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": true,
- "prefetch_on_access": false,
- "path": "system.cpu1.icache",
- "mshrs": 4,
- "name": "icache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 1
- },
- "function_trace": false,
- "do_checkpoint_insts": true,
- "cxx_class": "AtomicSimpleCPU",
- "max_loads_all_threads": 0,
- "system": "system",
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "cpu_id": 1,
- "width": 1,
- "checker": null,
- "eventq_index": 0,
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- },
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- },
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- },
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- },
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- },
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- "type": "LRU",
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- },
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- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu3.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
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- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- }
- ],
- "multi_thread": false,
- "exit_on_work_items": false,
- "work_item_id": -1,
- "num_work_ids": 16
- },
- "time_sync_period": 100000000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 100000000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": false
-}
\ No newline at end of file
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout: Broken pipe
-stdout: Broken pipe
+++ /dev/null
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jun 12 2016 19:14:13
-gem5 started Jun 12 2016 19:14:35
-gem5 executing on zizzer, pid 29714
-command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1104001 # Simulator instruction rate (inst/s)
-host_op_rate 1103987 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 138004981 # Simulator tick rate (ticks/s)
-host_mem_usage 246580 # Number of bytes of host memory used
-host_seconds 1.81 # Real time elapsed on the host
-sim_insts 2000004 # Number of instructions simulated
-sim_ops 2000004 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.itb.fetch_hits 500019 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_accesses 500032 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 500032 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 500001 # Number of instructions committed
-system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 474689 # number of integer instructions
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu0.num_mem_refs 180793 # number of memory refs
-system.cpu0.num_load_insts 124443 # Number of load instructions
-system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 500032 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.Branches 59023 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
-system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
-system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu0.dcache.writebacks::total 29 # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits
-system.cpu0.icache.overall_hits::total 499556 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu0.icache.writebacks::total 152 # number of writebacks
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.write_hits 56340 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_accesses 56350 # DTB write accesses
-system.cpu1.dtb.data_hits 180775 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_accesses 180793 # DTB accesses
-system.cpu1.itb.fetch_hits 500019 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500032 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 500032 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 500001 # Number of instructions committed
-system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474689 # number of integer instructions
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu1.num_mem_refs 180793 # number of memory refs
-system.cpu1.num_load_insts 124443 # Number of load instructions
-system.cpu1.num_store_insts 56350 # Number of store instructions
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 500032 # Number of busy cycles
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.Branches 59023 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500019 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits
-system.cpu1.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
-system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu1.dcache.writebacks::total 29 # number of writebacks
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits
-system.cpu1.icache.overall_hits::total 499556 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu1.icache.writebacks::total 152 # number of writebacks
-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.fetch_acv 0 # ITB acv
-system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.write_hits 56340 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_accesses 56350 # DTB write accesses
-system.cpu2.dtb.data_hits 180775 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180793 # DTB accesses
-system.cpu2.itb.fetch_hits 500019 # ITB hits
-system.cpu2.itb.fetch_misses 13 # ITB misses
-system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500032 # ITB accesses
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.read_acv 0 # DTB read access violations
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.write_acv 0 # DTB write access violations
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles 500032 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 500001 # Number of instructions committed
-system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu2.num_func_calls 14357 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474689 # number of integer instructions
-system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180793 # number of memory refs
-system.cpu2.num_load_insts 124443 # Number of load instructions
-system.cpu2.num_store_insts 56350 # Number of store instructions
-system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 500032 # Number of busy cycles
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.Branches 59023 # Number of branches fetched
-system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500019 # Class of executed instruction
-system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
-system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu2.dcache.writebacks::total 29 # number of writebacks
-system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits
-system.cpu2.icache.overall_hits::total 499556 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu2.icache.writebacks::total 152 # number of writebacks
-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.fetch_acv 0 # ITB acv
-system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124435 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124443 # DTB read accesses
-system.cpu3.dtb.write_hits 56340 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_accesses 56350 # DTB write accesses
-system.cpu3.dtb.data_hits 180775 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180793 # DTB accesses
-system.cpu3.itb.fetch_hits 500019 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500032 # ITB accesses
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.pwrStateResidencyTicks::ON 250015500 # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles 500032 # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 500001 # Number of instructions committed
-system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474689 # number of integer instructions
-system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180793 # number of memory refs
-system.cpu3.num_load_insts 124443 # Number of load instructions
-system.cpu3.num_store_insts 56350 # Number of store instructions
-system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 500032 # Number of busy cycles
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59023 # Number of branches fetched
-system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 500019 # Class of executed instruction
-system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
-system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu3.dcache.writebacks::total 29 # number of writebacks
-system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu3.icache.tags.replacements 152 # number of replacements
-system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses
-system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits
-system.cpu3.icache.overall_hits::total 499556 # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu3.icache.writebacks::total 152 # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 39936 # Number of tag accesses
-system.l2c.tags.data_accesses 39936 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu0.data 9 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu1.data 9 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu2.data 9 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 60 # number of overall hits
-system.l2c.overall_hits::cpu3.data 9 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu0.data 454 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu1.data 454 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu2.data 454 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 403 # number of overall misses
-system.l2c.overall_misses::cpu3.data 454 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.membus.snoop_filter.tot_requests 3428 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3428 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3428 # Request fanout histogram
-system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250015500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4556 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram
-
----------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-exit_on_work_items=false
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-readfile=
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=system.cpu0.workload
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu0.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu0.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=system.cpu1.workload
-dcache_port=system.cpu1.dcache.cpu_side
-icache_port=system.cpu1.icache.cpu_side
-
-[system.cpu1.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu1.dcache_port
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu1.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu1.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu1.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu1.icache_port
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu1.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu1.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu1.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu2]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=2
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu2.interrupts
-isa=system.cpu2.isa
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu2.tracer
-workload=system.cpu2.workload
-dcache_port=system.cpu2.dcache.cpu_side
-icache_port=system.cpu2.icache.cpu_side
-
-[system.cpu2.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu2.dcache_port
-mem_side=system.toL2Bus.slave[5]
-
-[system.cpu2.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu2.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu2.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu2.icache_port
-mem_side=system.toL2Bus.slave[4]
-
-[system.cpu2.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu2.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu2.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu2.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu2.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu2.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu3]
-type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=3
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu3.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu3.interrupts
-isa=system.cpu3.isa
-itb=system.cpu3.itb
-max_insts_all_threads=0
-max_insts_any_thread=500000
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu3.tracer
-workload=system.cpu3.workload
-dcache_port=system.cpu3.dcache.cpu_side
-icache_port=system.cpu3.icache.cpu_side
-
-[system.cpu3.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu3.dcache_port
-mem_side=system.toL2Bus.slave[7]
-
-[system.cpu3.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu3.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu3.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu3.icache_port
-mem_side=system.toL2Bus.slave[6]
-
-[system.cpu3.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu3.interrupts]
-type=AlphaInterrupts
-eventq_index=0
-
-[system.cpu3.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu3.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu3.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu3.workload]
-type=EioProcess
-chkpt=
-errout=cerr
-eventq_index=0
-file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-input=cin
-kvmInSE=false
-max_stack_size=67108864
-output=cout
-system=system
-useArchPT=false
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.system_port system.l2c.mem_side
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:134217727
-port=system.membus.master[0]
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
+++ /dev/null
-{
- "name": null,
- "sim_quantum": 0,
- "system": {
- "kernel": "",
- "mmap_using_noreserve": false,
- "kernel_addr_check": true,
- "membus": {
- "point_of_coherency": true,
- "system": "system",
- "response_latency": 2,
- "cxx_class": "CoherentXBar",
- "forward_latency": 4,
- "clk_domain": "system.clk_domain",
- "width": 16,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "master": {
- "peer": [
- "system.physmem.port"
- ],
- "role": "MASTER"
- },
- "type": "CoherentXBar",
- "frontend_latency": 3,
- "slave": {
- "peer": [
- "system.system_port",
- "system.l2c.mem_side"
- ],
- "role": "SLAVE"
- },
- "p_state_clk_gate_min": 1000,
- "snoop_filter": {
- "name": "snoop_filter",
- "system": "system",
- "max_capacity": 8388608,
- "eventq_index": 0,
- "cxx_class": "SnoopFilter",
- "path": "system.membus.snoop_filter",
- "type": "SnoopFilter",
- "lookup_latency": 1
- },
- "power_model": null,
- "path": "system.membus",
- "snoop_response_latency": 4,
- "name": "membus",
- "p_state_clk_gate_bins": 20,
- "use_default_range": false
- },
- "symbolfile": "",
- "l2c": {
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 20,
- "cxx_class": "Cache",
- "size": 4194304,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.l2c.tags",
- "hit_latency": 20,
- "block_size": 64,
- "type": "LRU",
- "size": 4194304
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.membus.slave[1]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 20,
- "tgts_per_mshr": 12,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.l2c",
- "mshrs": 20,
- "name": "l2c",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 8
- },
- "readfile": "",
- "thermal_model": null,
- "cxx_class": "System",
- "work_begin_cpu_id_exit": -1,
- "load_offset": 0,
- "work_begin_exit_count": 0,
- "p_state_clk_gate_min": 1000,
- "memories": [
- "system.physmem"
- ],
- "work_begin_ckpt_count": 0,
- "clk_domain": {
- "name": "clk_domain",
- "clock": [
- 1000
- ],
- "init_perf_level": 0,
- "voltage_domain": "system.voltage_domain",
- "eventq_index": 0,
- "cxx_class": "SrcClockDomain",
- "path": "system.clk_domain",
- "type": "SrcClockDomain",
- "domain_id": -1
- },
- "mem_ranges": [],
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "dvfs_handler": {
- "enable": false,
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- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[5]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.cpu2.dcache",
- "mshrs": 4,
- "name": "dcache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 4
- },
- "isa": [
- {
- "name": "isa",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu2.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu2.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- },
- {
- "do_statistics_insts": true,
- "numThreads": 1,
- "itb": {
- "name": "itb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu3.itb",
- "type": "AlphaTLB",
- "size": 48
- },
- "system": "system",
- "icache": {
- "cpu_side": {
- "peer": "system.cpu3.icache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 32768,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 1,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu3.icache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 32768
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[6]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": true,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": true,
- "prefetch_on_access": false,
- "path": "system.cpu3.icache",
- "mshrs": 4,
- "name": "icache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 1
- },
- "function_trace": false,
- "do_checkpoint_insts": true,
- "cxx_class": "TimingSimpleCPU",
- "max_loads_all_threads": 0,
- "clk_domain": "system.cpu_clk_domain",
- "function_trace_start": 0,
- "cpu_id": 3,
- "checker": null,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "do_quiesce": true,
- "type": "TimingSimpleCPU",
- "profile": 0,
- "icache_port": {
- "peer": "system.cpu3.icache.cpu_side",
- "role": "MASTER"
- },
- "p_state_clk_gate_bins": 20,
- "p_state_clk_gate_min": 1000,
- "interrupts": [
- {
- "eventq_index": 0,
- "path": "system.cpu3.interrupts",
- "type": "AlphaInterrupts",
- "name": "interrupts",
- "cxx_class": "AlphaISA::Interrupts"
- }
- ],
- "dcache_port": {
- "peer": "system.cpu3.dcache.cpu_side",
- "role": "MASTER"
- },
- "socket_id": 0,
- "power_model": null,
- "max_insts_all_threads": 0,
- "path": "system.cpu3",
- "max_loads_any_thread": 0,
- "switched_out": false,
- "workload": [
- {
- "name": "workload",
- "output": "cout",
- "chkpt": "",
- "errout": "cerr",
- "kvmInSE": false,
- "system": "system",
- "useArchPT": false,
- "eventq_index": 0,
- "file": "/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz",
- "cxx_class": "EioProcess",
- "path": "system.cpu3.workload",
- "max_stack_size": 67108864,
- "type": "EioProcess",
- "input": "cin"
- }
- ],
- "name": "cpu3",
- "dtb": {
- "name": "dtb",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::TLB",
- "path": "system.cpu3.dtb",
- "type": "AlphaTLB",
- "size": 64
- },
- "simpoint_start_insts": [],
- "max_insts_any_thread": 500000,
- "progress_interval": 0,
- "branchPred": null,
- "dcache": {
- "cpu_side": {
- "peer": "system.cpu3.dcache_port",
- "role": "SLAVE"
- },
- "clusivity": "mostly_incl",
- "prefetcher": null,
- "system": "system",
- "write_buffers": 8,
- "response_latency": 2,
- "cxx_class": "Cache",
- "size": 32768,
- "tags": {
- "name": "tags",
- "p_state_clk_gate_min": 1000,
- "eventq_index": 0,
- "p_state_clk_gate_bins": 20,
- "default_p_state": "UNDEFINED",
- "clk_domain": "system.cpu_clk_domain",
- "power_model": null,
- "sequential_access": false,
- "assoc": 4,
- "cxx_class": "LRU",
- "p_state_clk_gate_max": 1000000000000,
- "path": "system.cpu3.dcache.tags",
- "hit_latency": 2,
- "block_size": 64,
- "type": "LRU",
- "size": 32768
- },
- "clk_domain": "system.cpu_clk_domain",
- "max_miss_count": 0,
- "eventq_index": 0,
- "default_p_state": "UNDEFINED",
- "p_state_clk_gate_max": 1000000000000,
- "mem_side": {
- "peer": "system.toL2Bus.slave[7]",
- "role": "MASTER"
- },
- "type": "Cache",
- "writeback_clean": false,
- "p_state_clk_gate_min": 1000,
- "hit_latency": 2,
- "tgts_per_mshr": 20,
- "demand_mshr_reserve": 1,
- "power_model": null,
- "addr_ranges": [
- "0:18446744073709551615"
- ],
- "is_read_only": false,
- "prefetch_on_access": false,
- "path": "system.cpu3.dcache",
- "mshrs": 4,
- "name": "dcache",
- "p_state_clk_gate_bins": 20,
- "sequential_access": false,
- "assoc": 4
- },
- "isa": [
- {
- "name": "isa",
- "system": "system",
- "eventq_index": 0,
- "cxx_class": "AlphaISA::ISA",
- "path": "system.cpu3.isa",
- "type": "AlphaISA"
- }
- ],
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu3.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- }
- }
- ],
- "multi_thread": false,
- "exit_on_work_items": false,
- "work_item_id": -1,
- "num_work_ids": 16
- },
- "time_sync_period": 100000000000,
- "eventq_index": 0,
- "time_sync_spin_threshold": 100000000,
- "cxx_class": "Root",
- "path": "root",
- "time_sync_enable": false,
- "type": "Root",
- "full_system": false
-}
\ No newline at end of file
+++ /dev/null
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-
-gzip: stdout:
-gzip: stdout: Broken pipe
-stdout: Broken pipe
+++ /dev/null
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jun 12 2016 19:14:13
-gem5 started Jun 12 2016 19:14:35
-gem5 executing on zizzer, pid 29705
-command line: /z/stever/hg/gem5/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re /z/stever/hg/gem5/tests/testing/../run.py quick/se/30.eio-mp/alpha/eio/simple-timing-mp
-
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 734771500 because a thread reached the max instruction count
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000735 # Number of seconds simulated
-sim_ticks 734771500 # Number of ticks simulated
-final_tick 734771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 583455 # Simulator instruction rate (inst/s)
-host_op_rate 583451 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 214352932 # Simulator tick rate (ticks/s)
-host_mem_usage 246584 # Number of bytes of host memory used
-host_seconds 3.43 # Real time elapsed on the host
-sim_insts 1999973 # Number of instructions simulated
-sim_ops 1999973 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 219392 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35102069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39544266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35102069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39544266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35102069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39544266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35102069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39544266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 298585343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35102069 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35102069 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35102069 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35102069 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 140408277 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35102069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39544266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35102069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39544266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35102069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39544266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35102069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39544266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 298585343 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.itb.fetch_hits 500020 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_accesses 500033 # ITB accesses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 1469543 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 500001 # Number of instructions committed
-system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu0.num_func_calls 14357 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 474689 # number of integer instructions
-system.cpu0.num_fp_insts 32 # number of float instructions
-system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu0.num_mem_refs 180793 # number of memory refs
-system.cpu0.num_load_insts 124443 # Number of load instructions
-system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1469543 # Number of busy cycles
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.Branches 59023 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 500019 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 61 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 272.993368 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 272.993368 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.533190 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.533190 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits
-system.cpu0.dcache.overall_hits::total 180312 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses
-system.cpu0.dcache.overall_misses::total 463 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19964000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 19964000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8760000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 8760000 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 28724000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 28724000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 28724000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 28724000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 61617.283951 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 61617.283951 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 63021.582734 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 63021.582734 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62038.876890 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 62038.876890 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 62038.876890 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 62038.876890 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu0.dcache.writebacks::total 29 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19640000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19640000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8621000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8621000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28261000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 28261000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28261000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 28261000 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 60617.283951 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 60617.283951 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 62021.582734 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62021.582734 # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 61038.876890 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 61038.876890 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements 152 # number of replacements
-system.cpu0.icache.tags.tagsinuse 216.071308 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.071308 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422014 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.422014 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits
-system.cpu0.icache.overall_hits::total 499557 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
-system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26179500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 26179500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 26179500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 26179500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 26179500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 26179500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 56543.196544 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 56543.196544 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 56543.196544 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 56543.196544 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 56543.196544 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 56543.196544 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu0.icache.writebacks::total 152 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 25716500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 25716500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 25716500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 25716500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 25716500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 25716500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 55543.196544 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 55543.196544 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 55543.196544 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 55543.196544 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 55543.196544 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 55543.196544 # average overall mshr miss latency
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.write_hits 56339 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_accesses 56349 # DTB write accesses
-system.cpu1.dtb.data_hits 180774 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.itb.fetch_hits 500014 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 500027 # ITB accesses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.workload.num_syscalls 18 # Number of system calls
-system.cpu1.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 1469543 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 499995 # Number of instructions committed
-system.cpu1.committedOps 499995 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 474683 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu1.num_func_calls 14357 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 474683 # number of integer instructions
-system.cpu1.num_fp_insts 32 # number of float instructions
-system.cpu1.num_int_register_reads 654276 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 371538 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu1.num_mem_refs 180792 # number of memory refs
-system.cpu1.num_load_insts 124443 # Number of load instructions
-system.cpu1.num_store_insts 56349 # Number of store instructions
-system.cpu1.num_idle_cycles 0 # Number of idle cycles
-system.cpu1.num_busy_cycles 1469543 # Number of busy cycles
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.Branches 59022 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu1.op_class::IntAlu 300383 60.08% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction
-system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 500013 # Class of executed instruction
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.tags.replacements 61 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 272.990534 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 272.990534 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.533185 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.533185 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits
-system.cpu1.dcache.overall_hits::total 180311 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses
-system.cpu1.dcache.overall_misses::total 463 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 19964000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 19964000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8760500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 8760500 # number of WriteReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 28724500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 28724500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 28724500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 28724500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 61617.283951 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 61617.283951 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 63025.179856 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 63025.179856 # average WriteReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 62039.956803 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 62039.956803 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 62039.956803 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 62039.956803 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu1.dcache.writebacks::total 29 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 19640000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 19640000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 8621500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 8621500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 28261500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 28261500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 28261500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 28261500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 60617.283951 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 60617.283951 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 62025.179856 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 62025.179856 # average WriteReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 61039.956803 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 61039.956803 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.tags.replacements 152 # number of replacements
-system.cpu1.icache.tags.tagsinuse 216.069189 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 1078.943844 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.069189 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422010 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.422010 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses
-system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 499551 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 499551 # number of overall hits
-system.cpu1.icache.overall_hits::total 499551 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses
-system.cpu1.icache.overall_misses::total 463 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 26186000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 26186000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 26186000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 26186000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 26186000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 26186000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 500014 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 500014 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 500014 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 500014 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 500014 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 500014 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 56557.235421 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 56557.235421 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 56557.235421 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 56557.235421 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 56557.235421 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 56557.235421 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu1.icache.writebacks::total 152 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 25723000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 25723000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 25723000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 25723000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 25723000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 25723000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 55557.235421 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 55557.235421 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 55557.235421 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 55557.235421 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 55557.235421 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 55557.235421 # average overall mshr miss latency
-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.fetch_acv 0 # ITB acv
-system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 124435 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.write_hits 56339 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.data_hits 180774 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_accesses 180792 # DTB accesses
-system.cpu2.itb.fetch_hits 500009 # ITB hits
-system.cpu2.itb.fetch_misses 13 # ITB misses
-system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_accesses 500022 # ITB accesses
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.read_acv 0 # DTB read access violations
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.write_acv 0 # DTB write access violations
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.workload.num_syscalls 18 # Number of system calls
-system.cpu2.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles 1469543 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 499990 # Number of instructions committed
-system.cpu2.committedOps 499990 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 474678 # Number of integer alu accesses
-system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu2.num_func_calls 14357 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 474678 # number of integer instructions
-system.cpu2.num_fp_insts 32 # number of float instructions
-system.cpu2.num_int_register_reads 654270 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 371533 # number of times the integer registers were written
-system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu2.num_mem_refs 180791 # number of memory refs
-system.cpu2.num_load_insts 124442 # Number of load instructions
-system.cpu2.num_store_insts 56349 # Number of store instructions
-system.cpu2.num_idle_cycles 0 # Number of idle cycles
-system.cpu2.num_busy_cycles 1469543 # Number of busy cycles
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.Branches 59022 # Number of branches fetched
-system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu2.op_class::IntAlu 300379 60.07% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu2.op_class::MemRead 124442 24.89% 88.73% # Class of executed instruction
-system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 500008 # Class of executed instruction
-system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.tags.replacements 61 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 272.987788 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 272.987788 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.533179 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.533179 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses
-system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 180311 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 180311 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 180311 # number of overall hits
-system.cpu2.dcache.overall_hits::total 180311 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses
-system.cpu2.dcache.overall_misses::total 463 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 19964000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 19964000 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 8760000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 8760000 # number of WriteReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 28724000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 28724000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 28724000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 28724000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 180774 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 180774 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 61617.283951 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 61617.283951 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 63021.582734 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 63021.582734 # average WriteReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 62038.876890 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 62038.876890 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 62038.876890 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 62038.876890 # average overall miss latency
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu2.dcache.writebacks::total 29 # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 19640000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 19640000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 8621000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 8621000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 28261000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 28261000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 28261000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 28261000 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 60617.283951 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 60617.283951 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 62021.582734 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 62021.582734 # average WriteReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 61038.876890 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 61038.876890 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 61038.876890 # average overall mshr miss latency
-system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu2.icache.tags.replacements 152 # number of replacements
-system.cpu2.icache.tags.tagsinuse 216.067062 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs 1078.933045 # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.067062 # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422006 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total 0.422006 # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses
-system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses
-system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 499546 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 499546 # number of overall hits
-system.cpu2.icache.overall_hits::total 499546 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses
-system.cpu2.icache.overall_misses::total 463 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 26191500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 26191500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 26191500 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 26191500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 26191500 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 26191500 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 500009 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 500009 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 500009 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 500009 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 500009 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 500009 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 56569.114471 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 56569.114471 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 56569.114471 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 56569.114471 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 56569.114471 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 56569.114471 # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu2.icache.writebacks::total 152 # number of writebacks
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 25728500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 25728500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 25728500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 25728500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 25728500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 25728500 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 55569.114471 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 55569.114471 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 55569.114471 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 55569.114471 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 55569.114471 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 55569.114471 # average overall mshr miss latency
-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.fetch_acv 0 # ITB acv
-system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.read_hits 124433 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_accesses 124441 # DTB read accesses
-system.cpu3.dtb.write_hits 56339 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.data_hits 180772 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_accesses 180790 # DTB accesses
-system.cpu3.itb.fetch_hits 500006 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_accesses 500019 # ITB accesses
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.workload.num_syscalls 18 # Number of system calls
-system.cpu3.pwrStateResidencyTicks::ON 734771500 # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles 1469543 # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 499987 # Number of instructions committed
-system.cpu3.committedOps 499987 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 474675 # Number of integer alu accesses
-system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses
-system.cpu3.num_func_calls 14357 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 474675 # number of integer instructions
-system.cpu3.num_fp_insts 32 # number of float instructions
-system.cpu3.num_int_register_reads 654265 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 371530 # number of times the integer registers were written
-system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu3.num_mem_refs 180790 # number of memory refs
-system.cpu3.num_load_insts 124441 # Number of load instructions
-system.cpu3.num_store_insts 56349 # Number of store instructions
-system.cpu3.num_idle_cycles 0 # Number of idle cycles
-system.cpu3.num_busy_cycles 1469543 # Number of busy cycles
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.Branches 59022 # Number of branches fetched
-system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction
-system.cpu3.op_class::IntAlu 300377 60.07% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction
-system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction
-system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 500005 # Class of executed instruction
-system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.tags.replacements 61 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 272.985038 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 272.985038 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.533174 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.533174 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses
-system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 180309 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 180309 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 180309 # number of overall hits
-system.cpu3.dcache.overall_hits::total 180309 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses
-system.cpu3.dcache.overall_misses::total 463 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 19964500 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 19964500 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 8760000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 8760000 # number of WriteReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 28724500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 28724500 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 28724500 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 28724500 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 180772 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data 180772 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 61618.827160 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 61618.827160 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 63021.582734 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 63021.582734 # average WriteReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 62039.956803 # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 62039.956803 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 62039.956803 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 62039.956803 # average overall miss latency
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks
-system.cpu3.dcache.writebacks::total 29 # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 139 # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data 463 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data 463 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 19640500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 19640500 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 8621000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 8621000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 28261500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 28261500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 28261500 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 28261500 # number of overall MSHR miss cycles
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-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 60618.827160 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 60618.827160 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 62021.582734 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 62021.582734 # average WriteReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 61039.956803 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 61039.956803 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 61039.956803 # average overall mshr miss latency
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-system.cpu3.icache.tags.tagsinuse 216.064909 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 499543 # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 1078.926566 # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.064909 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422002 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.422002 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 500469 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 500469 # Number of data accesses
-system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.cpu3.icache.ReadReq_hits::cpu3.inst 499543 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 499543 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 499543 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 499543 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 499543 # number of overall hits
-system.cpu3.icache.overall_hits::total 499543 # number of overall hits
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-system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses
-system.cpu3.icache.overall_misses::total 463 # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 26196000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total 26196000 # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst 26196000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total 26196000 # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst 26196000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total 26196000 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 500006 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 500006 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst 500006 # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total 500006 # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst 500006 # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total 500006 # number of overall (read+write) accesses
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-system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 56578.833693 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 56578.833693 # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 56578.833693 # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 56578.833693 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 56578.833693 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 56578.833693 # average overall miss latency
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.icache.writebacks::writebacks 152 # number of writebacks
-system.cpu3.icache.writebacks::total 152 # number of writebacks
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 463 # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 25733000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total 25733000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 25733000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 25733000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 25733000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 25733000 # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 55578.833693 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 55578.833693 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 55578.833693 # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
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-system.l2c.tags.tagsinuse 1939.822021 # Cycle average of tags in use
-system.l2c.tags.total_refs 1068 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 17.160172 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 264.601415 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 216.071438 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 264.598662 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 216.069262 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 264.595900 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 216.067106 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 264.593110 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 216.064956 # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu2.data 0.003297 # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 39936 # Number of tag accesses
-system.l2c.tags.data_accesses 39936 # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits
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-system.l2c.overall_mshr_miss_latency::total 173181500 # number of overall MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.870410 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.972222 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.925486 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.870410 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data 0.980562 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.925486 # mshr miss rate for overall accesses
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50510.791367 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50514.388489 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50510.791367 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50514.388489 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 50512.589928 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50513.647643 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50527.295285 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50542.183623 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50555.831266 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50534.739454 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50503.174603 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50504.761905 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50503.571429 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50513.647643 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50505.506608 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50527.295285 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50506.607930 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50542.183623 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50505.506608 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50555.831266 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 50507.709251 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 50519.690782 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50513.647643 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50505.506608 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50527.295285 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50506.607930 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50542.183623 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50505.506608 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50555.831266 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 50507.709251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 50519.690782 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 3442 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 2872 # Transaction distribution
-system.membus.trans_dist::ReadExReq 556 # Transaction distribution
-system.membus.trans_dist::ReadExResp 556 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3442 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 3442 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 3442 # Request fanout histogram
-system.membus.reqLayer0.occupancy 3471468 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 17140000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 2.3 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 734771500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 0 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3704 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 3704 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3704 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3002000 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-# Copyright (c) 2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Lisa Hsu
-
-require_sim_object("EioProcess")
-
-process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
-
-for i in xrange(nb_cores):
- root.system.cpu[i].workload = process()
- root.system.cpu[i].max_insts_any_thread = 500000
projects / gem5.git / commitdiff