revert submodules/specials/clock_domains syntax

diff --git a/miscope/mila.py b/miscope/mila.py
index fe0c014297549399d5cf79dd40c0079aa11e4a55..abf8e79c9e63555624b193bd1ae31c8c96664c0a 100644 (file)
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -67,15 +67,15 @@ class MiLa(Module, AutoCSR):
                                sink.dat.eq(dat)
                        ]
 
-               self.trigger = trigger = Trigger(self.width, self.ports)
-               self.recorder = recorder = Recorder(self.width, self.depth)
+               self.submodules.trigger = trigger = Trigger(self.width, self.ports)
+               self.submodules.recorder = recorder = Recorder(self.width, self.depth)
                self.comb += [
                        sink.connect(trigger.sink),
                        trigger.source.connect(recorder.trig_sink)
                ]
 
                if self.with_rle:
-                       self.rle = rle = RunLengthEncoder(self.width)
+                       self.submodules.rle = rle = RunLengthEncoder(self.width)
                        self.comb += [
                                sink.connect(rle.sink),
                                rle.source.connect(recorder.dat_sink)

diff --git a/miscope/trigger.py b/miscope/trigger.py
index d27fa65ca487e50ea081273833908dcda95a8173..6e795f52fc27924973e743d16baf0e1e034b755a 100644 (file)
--- a/miscope/trigger.py
+++ b/miscope/trigger.py
@@ -124,9 +124,9 @@ class Trigger(Module, AutoCSR):
                self.width = width
                self.ports = ports
 
-               self.sum = Sum(len(ports))
+               self.submodules.sum = Sum(len(ports))
                for i, port in enumerate(ports):
-                       setattr(self, "port"+str(i), port)
+                       setattr(self.submodules, "port"+str(i), port)
 
                self.sink   = Record(dat_layout(width))
                self.source = self.sum.source

diff --git a/miscope/uart2wishbone.py b/miscope/uart2wishbone.py
index c32bde1e51ef2c805d73640aa696f65a2d3f09f7..e8e773f6dd8b813f89feed1f90988cadbd6c6736 100644 (file)
--- a/miscope/uart2wishbone.py
+++ b/miscope/uart2wishbone.py
@@ -39,6 +39,7 @@ class UART(Module, AutoCSR):
 
                self.rx = UARTRX(pads, tuning_word)
                self.tx = UARTTX(pads, tuning_word)
+               self.submodules += self.rx, self.tx
 
 class UARTPads:
        def __init__(self):
@@ -85,16 +86,17 @@ class UART2Wishbone(Module, AutoCSR):
                ###
                if share_uart:
                        self.uart_mux = UARTMux(pads)
-                       self.uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
+                       uart = UART(self.uart_mux.bridge_pads, clk_freq, baud)
                        self.shared_pads = self.uart_mux.shared_pads
                        self.comb += self.uart_mux.sel.eq(self._sel.storage)
                else:
-                       self.uart = UART(pads, clk_freq, baud)
+                       uart = UART(pads, clk_freq, baud)
+               self.submodules += uart
 
-               uart = self.uart
+               byte_counter = Counter(bits_sign=3)
+               word_counter = Counter(bits_sign=8)
+               self.submodules += byte_counter, word_counter
 
-               self.byte_counter = Counter(bits_sign=3)
-               self.word_counter = Counter(bits_sign=8)
 
                cmd = Signal(8)
                cmd_ce = Signal()
@@ -121,22 +123,24 @@ class UART2Wishbone(Module, AutoCSR):
                ]
 
                ###
-               self.fsm = fsm = InsertReset(FSM(reset_state="IDLE"))
-               self.timeout = Timeout(clk_freq//10)
+               fsm = InsertReset(FSM(reset_state="IDLE"))
+               timeout = Timeout(clk_freq//10)
+               self.submodules += fsm, timeout
+
                self.comb += [
-                       self.timeout.ce.eq(1),
-                       self.fsm.reset.eq(self.timeout.reached)
+                       timeout.ce.eq(1),
+                       fsm.reset.eq(timeout.reached)
                ]
                fsm.act("IDLE",
-                       self.timeout.reset.eq(1),
+                       timeout.reset.eq(1),
                        If(uart.rx.source.stb,
                                cmd_ce.eq(1),
                                If(     (uart.rx.source.d == self.cmds["write"]) |
                                        (uart.rx.source.d == self.cmds["read"]),
                                        NextState("RECEIVE_LENGTH")
                                ),
-                               self.byte_counter.reset.eq(1),
-                               self.word_counter.reset.eq(1)
+                               byte_counter.reset.eq(1),
+                               word_counter.reset.eq(1)
                        )
                )
                fsm.act("RECEIVE_LENGTH",
@@ -148,29 +152,29 @@ class UART2Wishbone(Module, AutoCSR):
                fsm.act("RECEIVE_ADDRESS",
                        If(uart.rx.source.stb,
                                address_ce.eq(1),
-                               self.byte_counter.ce.eq(1),
-                               If(self.byte_counter.value == 3,
+                               byte_counter.ce.eq(1),
+                               If(byte_counter.value == 3,
                                        If(cmd == self.cmds["write"],
                                                NextState("RECEIVE_DATA")
                                        ).Elif(cmd == self.cmds["read"],
                                                NextState("READ_DATA")
                                        ),
-                                       self.byte_counter.reset.eq(1),
+                                       byte_counter.reset.eq(1),
                                )
                        )
                )
                fsm.act("RECEIVE_DATA",
                        If(uart.rx.source.stb,
                                rx_data_ce.eq(1),
-                               self.byte_counter.ce.eq(1),
-                               If(self.byte_counter.value == 3,
+                               byte_counter.ce.eq(1),
+                               If(byte_counter.value == 3,
                                        NextState("WRITE_DATA"),
-                                       self.byte_counter.reset.eq(1)
+                                       byte_counter.reset.eq(1)
                                )
                        )
                )
                self.comb += [
-                       self.wishbone.adr.eq(address + self.word_counter.value),
+                       self.wishbone.adr.eq(address + word_counter.value),
                        self.wishbone.dat_w.eq(data),
                        self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
                ]
@@ -179,8 +183,8 @@ class UART2Wishbone(Module, AutoCSR):
                        self.wishbone.we.eq(1),
                        self.wishbone.cyc.eq(1),
                        If(self.wishbone.ack,
-                               self.word_counter.ce.eq(1),
-                               If(self.word_counter.value == (length-1),
+                               word_counter.ce.eq(1),
+                               If(word_counter.value == (length-1),
                                        NextState("IDLE")
                                ).Else(
                                        NextState("RECEIVE_DATA")
@@ -197,18 +201,18 @@ class UART2Wishbone(Module, AutoCSR):
                        )
                )
                self.comb += \
-                       chooser(data, self.byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
+                       chooser(data, byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
                fsm.act("SEND_DATA",
                        uart.tx.sink.stb.eq(1),
                        If(uart.tx.sink.ack,
-                               self.byte_counter.ce.eq(1),
-                               If(self.byte_counter.value == 3,
-                                       self.word_counter.ce.eq(1),
-                                       If(self.word_counter.value == (length-1),
+                               byte_counter.ce.eq(1),
+                               If(byte_counter.value == 3,
+                                       word_counter.ce.eq(1),
+                                       If(word_counter.value == (length-1),
                                                NextState("IDLE")
                                        ).Else(
                                                NextState("READ_DATA"),
-                                               self.byte_counter.reset.eq(1)
+                                               byte_counter.reset.eq(1)
                                        )
                                )
                        )

diff --git a/sim/tb_recorder_csr.py b/sim/tb_recorder_csr.py
index 5a882fa88e0a3913e87784045bfb8c95408c0f4e..368bb8004f405a66c9e286a7f99b48192f1c194b 100644 (file)
--- a/sim/tb_recorder_csr.py
+++ b/sim/tb_recorder_csr.py
@@ -81,10 +81,10 @@ class TB(Module):
                self.csr_base = 0
 
                # Recorder
-               self.recorder = Recorder(32, 1024)
-
+               self.submodules.recorder = Recorder(32, 1024)
+       
                # Csr
-               self.csrbankarray = csrgen.BankArray(self,
+               self.submodules.csrbankarray = csrgen.BankArray(self, 
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
 
                # Csr Master
@@ -93,16 +93,16 @@ class TB(Module):
 
                bus = Csr2Trans()
                regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-               self.master = csr.Initiator(csr_transactions(bus, regs))
+               self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
 
-               self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
+               self.submodules.csrcon = csr.Interconnect(self.master.bus,      self.csrbankarray.get_buses())
 
        # Recorder Data
        def recorder_data(self, selfp):
                selfp.recorder.dat_sink.stb = 1
                if not hasattr(self, "cnt"):
                        self.cnt = 0
-               self.cnt += 1
+               self.cnt += 1   
 
                selfp.recorder.dat_sink.dat =  self.cnt
 

diff --git a/sim/tb_rle.py b/sim/tb_rle.py
index 68ccf0dff184d775f0ffd5233f74176a731af564..1dd8e75c8c973c0569f789e804c05e8ec4040c24 100644 (file)
--- a/sim/tb_rle.py
+++ b/sim/tb_rle.py
@@ -26,7 +26,7 @@ class TB(Module):
        def __init__(self):
 
                # Rle
-               self.rle = storage.RunLengthEncoder(16, 32)
+               self.submodules.rle = storage.RunLengthEncoder(16, 32)
 
        def do_simulation(self, selfp):
                selfp.rle._r_enable.storage = 1

diff --git a/sim/tb_trigger_csr.py b/sim/tb_trigger_csr.py
index 66390a4456d55ea78916f026e39cca4ea4328995..ef74703b9ad408467d7f5d175e8dbb829ef2546d 100644 (file)
--- a/sim/tb_trigger_csr.py
+++ b/sim/tb_trigger_csr.py
@@ -66,10 +66,10 @@ class TB(Module):
                term1 = Term(32)
                term2 = Term(32)
                term3 = Term(32)
-               self.trigger = Trigger(32, [term0, term1, term2, term3])
+               self.submodules.trigger = Trigger(32, [term0, term1, term2, term3])
 
                # Csr
-               self.csrbankarray = csrgen.BankArray(self,
+               self.submodules.csrbankarray = csrgen.BankArray(self, 
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
 
                # Csr Master
@@ -78,9 +78,9 @@ class TB(Module):
 
                bus = Csr2Trans()
                regs = build_map(addrmap, bus.read_csr, bus.write_csr)
-               self.master = csr.Initiator(csr_transactions(bus, regs))
+               self.submodules.master = csr.Initiator(csr_transactions(bus, regs))
 
-               self.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
+               self.submodules.csrcon = csr.Interconnect(self.master.bus,      self.csrbankarray.get_buses())
 
                self.terms = [term0, term1, term2, term3]