Reduce delay between wishbone_write

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 508a35a7ded13bac87a9490aff0c58a2a32098ba..e90c19e7ab80651c14284d1d5d9ca2b0f3238567 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -196,9 +196,9 @@ module simsoctb;
 
       // Write
       wishbone_write(32'h10000000 >> 2, 32'h12345678);
-      #10000;
+      #2000;
       wishbone_write(32'h10000100 >> 2, 32'h00000000);
-      #10000;
+      #2000;
       wishbone_read(32'h10000000 >> 2, tmp);
       assert_equal_32(tmp, 32'h12345678);