[GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8.1-M...

This patch is adding the following instructions:

ASRL (reg)
LSLL (reg)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
	(ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
	* config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
	register pairs for doubleword quantities for ARMv8.1M-Mainline.
	* config/arm/thumb2.md (thumb2_asrl): New.
	(thumb2_lsll): Likewise.

2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4efbba67d890de29237300005e0f825a9c506bd2..2dadf5891e7d8ec1944477a103de7d7158bd4dbe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
+           Sudakshina Das  <sudi.das@arm.com>
+
+       * config/arm/arm.md (ashldi3): Generate thumb2_lsll for TARGET_HAVE_MVE.
+       (ashrdi3): Generate thumb2_asrl for TARGET_HAVE_MVE.
+       * config/arm/arm.c (arm_hard_regno_mode_ok): Allocate even odd
+       register pairs for doubleword quantities for ARMv8.1M-Mainline.
+       * config/arm/thumb2.md (thumb2_asrl): New.
+       (thumb2_lsll): Likewise.
+
 2020-01-17  Jakub Jelinek  <jakub@redhat.com>
 
        * config/arm/arm.c (cmse_nonsecure_call_inline_register_clear): Remove

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 57099cbc7fa901cf22ecb0232b4bb4f8689f46cd..6ead410d1a8b307a646fda57b37b884fae7d0ab0 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -24906,14 +24906,16 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 
   /* We allow almost any value to be stored in the general registers.
      Restrict doubleword quantities to even register pairs in ARM state
-     so that we can use ldrd.  Do not allow very large Neon structure
-     opaque modes in general registers; they would use too many.  */
+     so that we can use ldrd. The same restriction applies for MVE
+     in order to support Armv8.1-M Mainline instructions.
+     Do not allow very large Neon structure  opaque modes in general
+     registers; they would use too many.  */
   if (regno <= LAST_ARM_REGNUM)
     {
       if (ARM_NUM_REGS (mode) > 4)
        return false;
 
-      if (TARGET_THUMB2)
+      if (TARGET_THUMB2 && !TARGET_HAVE_MVE)
        return true;
 
       return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 528d134a7510c504cd3d7d7ffaefd24a40991ae3..315b04c4434c0a0d7dd572e432c213bc005782a3 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4399,6 +4399,22 @@
                    (match_operand:SI 2 "reg_or_int_operand")))]
   "TARGET_32BIT"
   "
+  if (TARGET_HAVE_MVE)
+    {
+      if (!reg_or_int_operand (operands[2], SImode))
+        operands[2] = force_reg (SImode, operands[2]);
+
+      /* Armv8.1-M Mainline double shifts are not expanded.  */
+      if (REG_P (operands[2]))
+       {
+         if (!reg_overlap_mentioned_p(operands[0], operands[1]))
+           emit_insn (gen_movdi (operands[0], operands[1]));
+
+         emit_insn (gen_thumb2_lsll (operands[0], operands[2]));
+         DONE;
+       }
+    }
+
   arm_emit_coreregs_64bit_shift (ASHIFT, operands[0], operands[1],
                                 operands[2], gen_reg_rtx (SImode),
                                 gen_reg_rtx (SImode));
@@ -4426,6 +4442,16 @@
                      (match_operand:SI 2 "reg_or_int_operand")))]
   "TARGET_32BIT"
   "
+  /* Armv8.1-M Mainline double shifts are not expanded.  */
+  if (TARGET_HAVE_MVE && REG_P (operands[2]))
+    {
+      if (!reg_overlap_mentioned_p(operands[0], operands[1]))
+       emit_insn (gen_movdi (operands[0], operands[1]));
+
+      emit_insn (gen_thumb2_asrl (operands[0], operands[2]));
+      DONE;
+    }
+
   arm_emit_coreregs_64bit_shift (ASHIFTRT, operands[0], operands[1],
                                 operands[2], gen_reg_rtx (SImode),
                                 gen_reg_rtx (SImode));

diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 3ca491126355c79e22c4924a489dfd407ee6d27a..a5986de4859a4241dbdcf1606bb16d56d9b0c58e 100644 (file)
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1626,3 +1626,19 @@
   }
   [(set_attr "predicable" "yes")]
 )
+
+(define_insn "thumb2_asrl"
+  [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+       (ashiftrt:DI (match_dup 0)
+                    (match_operand:SI 1 "arm_general_register_operand" "r")))]
+  "TARGET_HAVE_MVE"
+  "asrl%?\\t%Q0, %R0, %1"
+  [(set_attr "predicable" "yes")])
+
+(define_insn "thumb2_lsll"
+  [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+       (ashift:DI (match_dup 0)
+                  (match_operand:SI 1 "arm_general_register_operand" "r")))]
+  "TARGET_HAVE_MVE"
+  "lsll%?\\t%Q0, %R0, %1"
+  [(set_attr "predicable" "yes")])

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f7edad9a64ce5f4882f5137ed439c9f2f4fab3c8..9de42e4de428cb0a701c7a780631534da4e6b2f8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
+           Sudakshina Das  <sudi.das@arm.com>
+
+       * gcc.target/arm/armv8_1m-shift-reg_1.c: New test.
+
 2020-01-17  Jonathan Wakely  <jwakely@redhat.com>
 
        PR testsuite/93227

diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
new file mode 100644 (file)
index 0000000..a97e9d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-reg-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+
+long long longval2;
+int intval2;
+
+long long int
+asrl_reg ()
+{
+ return (longval2 >> intval2);
+}
+
+long long unsigned int
+lsll_reg (long long unsigned longval1, int intval1)
+{
+  return (longval1 << intval1);
+}
+
+/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */
+/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], r\[0-9\]" } } */