Moved GP_POR out of digital cells b/c it has delays

diff --git a/techlibs/greenpak4/cells_sim_ams.v b/techlibs/greenpak4/cells_sim_ams.v
index 370db897d5dba123a799212ce04651b1a47b0052..7f8b3de3ba2593d8a1289042c81714051e61b4dc 100644 (file)
--- a/techlibs/greenpak4/cells_sim_ams.v
+++ b/techlibs/greenpak4/cells_sim_ams.v
@@ -87,3 +87,24 @@ module GP_VREF(input VIN, output reg VOUT);
        parameter VREF = 0;
        //cannot simulate mixed signal IP
 endmodule
+
+module GP_POR(output reg RST_DONE);
+       parameter POR_TIME = 500;
+
+       initial begin
+               RST_DONE = 0;
+
+               if(POR_TIME == 4)
+                       #4000;
+               else if(POR_TIME == 500)
+                       #500000;
+               else begin
+                       $display("ERROR: bad POR_TIME for GP_POR cell");
+                       $finish;
+               end
+
+               RST_DONE = 1;
+
+       end
+
+endmodule

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index db5bd911213238800c84207798b84a1546130061..f8ab5bf3761eb6e653a4602538a12915292c0384 100644 (file)
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -378,27 +378,6 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 
 endmodule
 
-module GP_POR(output reg RST_DONE);
-       parameter POR_TIME = 500;
-
-       initial begin
-               RST_DONE = 0;
-
-               if(POR_TIME == 4)
-                       #4000;
-               else if(POR_TIME == 500)
-                       #500000;
-               else begin
-                       $display("ERROR: bad POR_TIME for GP_POR cell");
-                       $finish;
-               end
-
-               RST_DONE = 1;
-
-       end
-
-endmodule
-
 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 
        parameter OUTA_TAP = 1;