void SimpleCPU::CacheCompletionEvent::process()
{
- cpu->processCacheCompletion();
+ cpu->processCacheCompletion(read);
}
const char *
Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- memReq->reset(addr, sizeof(T), flags);
+ Fault fault;
- // translate to physical address
- Fault fault = xc->translateDataReadReq(memReq);
-
- // do functional access
- if (fault == No_Fault)
+ if (status() == DcacheMissStall) {
+ //Just do the functional access
fault = xc->read(memReq, data);
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
+ if (traceData) {
+ traceData->setAddr(addr);
+ if (fault == No_Fault)
+ traceData->setData(data);
+ }
+ return fault;
}
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ fault = xc->translateDataReadReq(memReq);
+
// if we have a cache, do cache access too
if (fault == No_Fault && dcacheInterface) {
memReq->cmd = Read;
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
+ cacheCompletionEvent.read = true;
memReq->completionEvent = &cacheCompletionEvent;
+ //May later want to pass the staticinst as well, so it can call
+ //it independantly
lastDcacheStall = curTick;
unscheduleTickEvent();
_status = DcacheMissStall;
}
+ else {
+ // do functional access
+ if (fault == No_Fault)
+ fault = xc->read(memReq, data);
+
+ if (traceData) {
+ traceData->setAddr(addr);
+ if (fault == No_Fault)
+ traceData->setData(data);
+ }
+ }
}
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
+ cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
unscheduleTickEvent();
void
-SimpleCPU::processCacheCompletion()
+SimpleCPU::processCacheCompletion(bool read)
{
switch (status()) {
case IcacheMissStall:
break;
case DcacheMissStall:
dcacheStallCycles += curTick - lastDcacheStall;
+ if (read) {
+ globalsi->execute(this,traceData);
+ }
_status = Running;
scheduleTickEvent(1);
break;
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && icacheInterface->doEvents()) {
+ cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastIcacheStall = curTick;
unscheduleTickEvent();
inst = htoa(inst);
StaticInstPtr<TheISA> si(inst);
+ globalsi = si;
+
traceData = Trace::getInstRecord(curTick, xc, this, si,
xc->regs.pc);
// Refcounted pointer to the one memory request.
MemReqPtr memReq;
+ StaticInstPtr<TheISA> globalsi;
+
class CacheCompletionEvent : public Event
{
private:
public:
CacheCompletionEvent(SimpleCPU *_cpu);
+ bool read;
+
virtual void process();
virtual const char *description();
};
Stats::Scalar<> dcacheStallCycles;
Counter lastDcacheStall;
- void processCacheCompletion();
+ void processCacheCompletion(bool read);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);