+2013-12-06 Ian Bolton <ian.bolton@arm.com>
+ Mark Mitchell <mark@codesourcery.com>
+
+ PR target/59091
+ * config/arm/arm.md (trap): New pattern.
+ * config/arm/types.md: Added a type for trap.
+
2013-12-06 Bernd Edlinger <bernd.edlinger@hotmail.de>
* expr.c (expand_assignment): Update bitregion_start and
(set_attr "type" "mov_reg")]
)
+(define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ ""
+ "*
+ if (TARGET_ARM)
+ return \".inst\\t0xe7f000f0\";
+ else
+ return \".inst\\t0xdeff\";
+ "
+ [(set (attr "length")
+ (if_then_else (eq_attr "is_thumb" "yes")
+ (const_int 2)
+ (const_int 4)))
+ (set_attr "type" "trap")
+ (set_attr "conds" "unconditional")]
+)
+
\f
;; Patterns to allow combination of arithmetic, cond code and shifts
; store2 store 2 words to memory from arm registers.
; store3 store 3 words to memory from arm registers.
; store4 store 4 (or more) words to memory from arm registers.
+; trap cause a trap in the kernel.
; udiv unsigned division.
; umaal unsigned multiply accumulate accumulate long.
; umlal unsigned multiply accumulate long.
store2,\
store3,\
store4,\
+ trap,\
udiv,\
umaal,\
umlal,\
+2013-12-06 Ian Bolton <ian.bolton@arm.com>
+ Mark Mitchell <mark@codesourcery.com>
+
+ PR target/59091
+ * gcc.target/arm/builtin-trap.c: New test.
+ * gcc.target/arm/thumb-builtin-trap.c: Likewise.
+
2013-12-06 Eric Botcazou <ebotcazou@adacore.com>
* gcc.target/sparc/pdistn.c: New test.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+
+void
+trap ()
+{
+ __builtin_trap ();
+}
+
+/* { dg-final { scan-assembler "0xe7f000f0" { target { arm_nothumb } } } } */
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mthumb" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+void
+trap ()
+{
+ __builtin_trap ();
+}
+
+/* { dg-final { scan-assembler "0xdeff" } } */