ARM: Implement a version of mcr and mrc that works in user mode.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index be0e639008011673b51cf44f934ea3d01f019ec1..2801ebedfa47b90b44e1b192b21b2000712b51b1 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -137,6 +137,8 @@ let {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+
+            // Write only.
           case MISCREG_TLBIALLIS:
           case MISCREG_TLBIMVAIS:
           case MISCREG_TLBIASIDIS:
@@ -157,6 +159,23 @@ let {{
                 return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
             }
 
+            // Read only in user mode.
+          case MISCREG_TPIDRURO:
+            if (isRead) {
+                return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
+            } else {
+                return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
+            }
+
+            // Read/write in user mode.
+          case MISCREG_TPIDRURW:
+            if (isRead) {
+                return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
+            } else {
+                return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
+            }
+
+            // Read/write, priveleged only.
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 7f9a5c171b96e74d0ab093928ce5ca01d10fa9ae..6b81853f135c13992a464c9ca35cd4e496b35b4f 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -614,6 +614,20 @@ let {{
     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
     exec_output += PredOpExecute.subst(mcr15Iop)
 
+    mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
+                                 { "code": "Dest = MiscOp1;",
+                                   "predicate_test": predicateTest }, [])
+    header_output += RegRegOpDeclare.subst(mrc15UserIop)
+    decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
+    exec_output += PredOpExecute.subst(mrc15UserIop)
+
+    mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
+                                 { "code": "MiscDest = Op1",
+                                   "predicate_test": predicateTest }, [])
+    header_output += RegRegOpDeclare.subst(mcr15UserIop)
+    decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
+    exec_output += PredOpExecute.subst(mcr15UserIop)
+
     enterxCode = '''
         FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
     '''