Fix tribuf test

diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
index ef426695926b73c20e00b0bb6b36c80ee25a5daf..d1e1b3108475a31312eeb523328c835399236260 100644 (file)
--- a/tests/ice40/tribuf.ys
+++ b/tests/ice40/tribuf.ys
@@ -2,7 +2,7 @@ read_verilog tribuf.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_