Revert "965: Fix color clamping issues"
authorIan Romanick <ian.d.romanick@intel.com>
Thu, 24 Jul 2008 15:39:51 +0000 (08:39 -0700)
committerIan Romanick <ian.d.romanick@intel.com>
Thu, 24 Jul 2008 15:40:22 +0000 (08:40 -0700)
This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d.  The
patch was applied incorrectly.  Actual fix coming soon.  Sorry for the
noise.

src/mesa/drivers/dri/i965/brw_vs_emit.c

index 8c7bc98c61b7e60243a6919e73efd4686fc0e2f5..7767d1369ceaeb9b0da9fb542183753a5bdd6185 100644 (file)
@@ -1160,29 +1160,9 @@ void brw_vs_emit(struct brw_vs_compile *c )
       }
 
       if (inst->DstReg.File == PROGRAM_OUTPUT
-          && inst->DstReg.Index != VERT_RESULT_HPOS
-          && c->output_regs[inst->DstReg.Index].used_in_src) {
-         /* Result color clamping.
-          * 
-          * When destination register is an output register and it's
-          * primary/secondary front/back color, we have to clamp the result
-          * to [0,1]. This is done by enabling the saturation bit for the
-          * last instruction.
-          * 
-          * We don't use brw_set_saturate() as it modifies
-          * p->current->header.saturate, which affects all the subsequent
-          * instructions. Instead, we directly modify the header of the last
-          * (already stored) instruction.
-          */
-         if (inst->DstReg.File == PROGRAM_OUTPUT) {
-            if ((inst->DstReg.Index == VERT_RESULT_COL0) ||
-                (inst->DstReg.Index == VERT_RESULT_COL1) ||
-                (inst->DstReg.Index == VERT_RESULT_BFC0) ||
-                (inst->DstReg.Index == VERT_RESULT_BFC1)) {            
-               p->store[p->nr_insn-1].header.saturate = 1;
-            }
-         }
-      }
+             &&inst->DstReg.Index != VERT_RESULT_HPOS
+             &&c->output_regs[inst->DstReg.Index].used_in_src)
+         brw_MOV(p, get_dst(c, inst->DstReg), dst);
 
       release_tmps(c);
    }