Use migen.fhdl.std

diff --git a/milkymist/asmicon/__init__.py b/milkymist/asmicon/__init__.py
index 828ccd642e67aa1143f65eeccad6fc3b5dffc933..5ea25c118e0b64ad28f6abd133e90cfff46476f8 100644 (file)
--- a/milkymist/asmicon/__init__.py
+++ b/milkymist/asmicon/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import dfi, asmibus
 
 from milkymist.asmicon.refresher import *

diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py
index 0e296fb0a26db43d006b382b8100929dd598141d..361631de698cf1ada98ed4e05d24ebee5f19f9e2 100644 (file)
--- a/milkymist/asmicon/bankmachine.py
+++ b/milkymist/asmicon/bankmachine.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM

diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index ae254418cdd18811b70b2932cf4696a2f1107a9a..9793c5516f6e4cee094766188379e651461061cf 100644 (file)
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.roundrobin import *
 from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM
@@ -26,7 +25,7 @@ class _CommandChooser(Module):
                self.want_reads = Signal()
                self.want_writes = Signal()
                # NB: cas_n/ras_n/we_n are 1 when stb is inactive
-               self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba), tagbits)
+               self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba), tagbits)
        
                ###
 
@@ -83,7 +82,7 @@ class _Steerer(Module):
 
 class _Datapath(Module):
        def __init__(self, timing_settings, command, dfi, hub):
-               tagbits = len(hub.tag_call)
+               tagbits = flen(hub.tag_call)
                
                rd_valid = Signal()
                rd_tag = Signal(tagbits)
@@ -136,7 +135,7 @@ class Multiplexer(Module):
        
                # Command choosing
                requests = [bm.cmd for bm in bank_machines]
-               tagbits = len(hub.tag_call)
+               tagbits = flen(hub.tag_call)
                choose_cmd = _CommandChooser(requests, tagbits)
                choose_req = _CommandChooser(requests, tagbits)
                self.comb += [

diff --git a/milkymist/asmicon/refresher.py b/milkymist/asmicon/refresher.py
index 3ad0334b3f074cf2cd16ba4e74ad985c65716f5d..cda70433e27e78245862788451bb720dec87fc1a 100644 (file)
--- a/milkymist/asmicon/refresher.py
+++ b/milkymist/asmicon/refresher.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 

diff --git a/milkymist/asmiprobe/__init__.py b/milkymist/asmiprobe/__init__.py
index c449357fc56ad290f73bab633f3d71ae1430bf4d..ca9f9851a43ce72b2c8ef5a098c3598ff91dc339 100644 (file)
--- a/milkymist/asmiprobe/__init__.py
+++ b/milkymist/asmiprobe/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 
 class ASMIprobe(Module):

diff --git a/milkymist/counteradc/__init__.py b/milkymist/counteradc/__init__.py
index b785ee08022cd3ce90acd91222bdc681cdf7542b..9df83c3523e560d608a3b6ea7ed07d7810b92a3c 100644 (file)
--- a/milkymist/counteradc/__init__.py
+++ b/milkymist/counteradc/__init__.py
@@ -1,5 +1,6 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+import collections
+
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import MultiReg

diff --git a/milkymist/dfii/__init__.py b/milkymist/dfii/__init__.py
index 2db5d56eff50bc2b35b65ce5efed551e52c59391..22a5bcd5e905bcc8d9280d54df84796941e94610 100644 (file)
--- a/milkymist/dfii/__init__.py
+++ b/milkymist/dfii/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import dfi
 from migen.bank.description import *
 
@@ -7,10 +6,10 @@ class PhaseInjector(Module, AutoCSR):
        def __init__(self, phase):
                self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
                self._command_issue = CSR()
-               self._address = CSRStorage(len(phase.address))
-               self._baddress = CSRStorage(len(phase.bank))
-               self._wrdata = CSRStorage(len(phase.wrdata))
-               self._rddata = CSRStatus(len(phase.rddata))
+               self._address = CSRStorage(flen(phase.address))
+               self._baddress = CSRStorage(flen(phase.bank))
+               self._wrdata = CSRStorage(flen(phase.wrdata))
+               self._rddata = CSRStatus(flen(phase.rddata))
        
                ###
 

diff --git a/milkymist/dvisampler/__init__.py b/milkymist/dvisampler/__init__.py
index 6819fb183d66b9ba3e49b44ff72b714b336d8655..5b74f53a9d04acb0936cc574f842456bb2be83d7 100644 (file)
--- a/milkymist/dvisampler/__init__.py
+++ b/milkymist/dvisampler/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import AutoCSR
 
 from milkymist.dvisampler.edid import EDID

diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
index d402ce0853669bd9d19e9302fc1e4f223c586ec1..a1fa46ebfbc2a283399af45e20d56e3ed77a633f 100644 (file)
--- a/milkymist/dvisampler/analysis.py
+++ b/milkymist/dvisampler/analysis.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
index 63a5b1ccb2f2f9bb706c9f0b6c742f1251ef1351..3a50b3d38cc1db3545c8558f3f352b2095189044 100644 (file)
--- a/milkymist/dvisampler/chansync.py
+++ b/milkymist/dvisampler/chansync.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len

diff --git a/milkymist/dvisampler/charsync.py b/milkymist/dvisampler/charsync.py
index bb55ea4babd1c7cb05fcbf76d07f05172adfbe90..92e38e9f542d0c2384f7bfa2f9a0c06a0f1feaf5 100644 (file)
--- a/milkymist/dvisampler/charsync.py
+++ b/milkymist/dvisampler/charsync.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
index be7f833f1c4f8a38162c528c1838e1b5cbaebb63..e718e4b1c40cab8058dfa1025469742b58c81e93 100644 (file)
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

diff --git a/milkymist/dvisampler/datacapture.py b/milkymist/dvisampler/datacapture.py
index fa0caab16a85150443d0dba58036ed0b3c32b881..8cb060c7e500839d54a9281d7f75f42c93bf9ab7 100644 (file)
--- a/milkymist/dvisampler/datacapture.py
+++ b/milkymist/dvisampler/datacapture.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 

diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py
index 3eb7786178952ebfaad9132f2d0fd4f73bd17abe..21d937ed87f536dbf060a030352e969b096fa8c9 100644 (file)
--- a/milkymist/dvisampler/debug.py
+++ b/milkymist/dvisampler/debug.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR

diff --git a/milkymist/dvisampler/decoding.py b/milkymist/dvisampler/decoding.py
index d051a86c5b0f85544123ef0f91303f988f5a1889..034f454358a3b1170398ccada9caa4642c5f2461 100644 (file)
--- a/milkymist/dvisampler/decoding.py
+++ b/milkymist/dvisampler/decoding.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.record import Record
 
 from milkymist.dvisampler.common import control_tokens, channel_layout

diff --git a/milkymist/dvisampler/dma.py b/milkymist/dvisampler/dma.py
index 1eddc4221a1ac4bda068d8a16f0c3500ca2a4a50..1a361b17fed0b81cc347835a90ec5057e9afa179 100644 (file)
--- a/milkymist/dvisampler/dma.py
+++ b/milkymist/dvisampler/dma.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.fsm import FSM
 from migen.bank.description import *
 from migen.bank.eventmanager import *

diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py
index f42b9dfdf40d63b2e613419e6ec4b03ed7e96193..c2726a4717c7a72e8bb66ef8c1943ac3699a2e43 100644 (file)
--- a/milkymist/dvisampler/edid.py
+++ b/milkymist/dvisampler/edid.py
@@ -1,6 +1,5 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Memory, Tristate
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
+from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM
 from migen.genlib.misc import chooser

diff --git a/milkymist/dvisampler/wer.py b/milkymist/dvisampler/wer.py
index 5e9a23800bbec31b75383db88d4a72103db58096..89d89a0ec37a35062f3e9f69e5d73025f4dc144c 100644 (file)
--- a/milkymist/dvisampler/wer.py
+++ b/milkymist/dvisampler/wer.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer

diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py
index 4161d6fbc2718de115eb7a91e95c820decdc559f..58ebfbc91d275a57d1f5bd67ef7bbfaf6fb24008 100644 (file)
--- a/milkymist/framebuffer/__init__.py
+++ b/milkymist/framebuffer/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.flow.network import *
 from migen.bank.description import CSRStorage, AutoCSR

diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
index 7fa5c9bd92fc5128df925e42cc74db99c4d70a0a..79ed0ad463869e3717815c5d8eb9171f38d86475 100644 (file)
--- a/milkymist/framebuffer/lib.py
+++ b/milkymist/framebuffer/lib.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.record import Record
 from migen.genlib.fifo import AsyncFIFO
 from migen.flow.actor import *

diff --git a/milkymist/gpio/__init__.py b/milkymist/gpio/__init__.py
index f2ac9abe45e26a73b3a56f67d19945107387bb00..d02332eca6bea9e37b8373f0ed9366f1766a732c 100644 (file)
--- a/milkymist/gpio/__init__.py
+++ b/milkymist/gpio/__init__.py
@@ -1,16 +1,15 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
 class GPIOIn(Module, AutoCSR):
        def __init__(self, signal):
-               self._r_in = CSRStatus(len(signal))
+               self._r_in = CSRStatus(flen(signal))
                self.specials += MultiReg(signal, self._r_in.status)
 
 class GPIOOut(Module, AutoCSR):
        def __init__(self, signal):
-               self._r_out = CSRStorage(len(signal))
+               self._r_out = CSRStorage(flen(signal))
                self.comb += signal.eq(self._r_out.storage)
 
 class Blinker(Module):

diff --git a/milkymist/identifier/__init__.py b/milkymist/identifier/__init__.py
index 3fc27422f2d9ce49ac4dc4f20fba4276ef594eff..ca792fd1bae88880c7b410815c3ec183b54f9b6d 100644 (file)
--- a/milkymist/identifier/__init__.py
+++ b/milkymist/identifier/__init__.py
@@ -1,7 +1,6 @@
 import re
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 
 def encode_version(version):

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 8792b01088d048768acde6ddc59dfb581d87dd76..35cf81cad27cad15a3c6eee56b4435742506e0b8 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import wishbone
 
 class LM32(Module):

diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py
index 9e1511f6c4e478135fed6f770ac02408f4f8ca21..e163c1bfe26198d5353006ff64b58c7b25dc9e3f 100644 (file)
--- a/milkymist/m1crg/__init__.py
+++ b/milkymist/m1crg/__init__.py
@@ -1,8 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 
 class M1CRG(Module, AutoCSR):

diff --git a/milkymist/minimac3/__init__.py b/milkymist/minimac3/__init__.py
index 308b0045f833cf3f6007c684c787b8599fb44a45..37efdd490a2dc2f1e9080492938c903ae02c2b92 100644 (file)
--- a/milkymist/minimac3/__init__.py
+++ b/milkymist/minimac3/__init__.py
@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.bus import wishbone

diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
index 705d2ae6129d7b8832512dd776647b1bc3804ead..241d6acf22361de1f712da3fecaebf68dc570e7a 100644 (file)
--- a/milkymist/norflash/__init__.py
+++ b/milkymist/norflash/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import wishbone
 from migen.genlib.misc import timeline
 
@@ -9,7 +8,7 @@ class NorFlash(Module):
        
                ###
 
-               adr_width = len(pads.adr) + 1
+               adr_width = flen(pads.adr) + 1
                self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1),
                        pads.ce_n.eq(0)]
                self.sync += timeline(self.bus.cyc & self.bus.stb, [

diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py
index 6f7b470d93d3c9a2a3333b308a916c732884fb79..bd684ce908f8a41ec6017a5594e44d7c31043693 100644 (file)
--- a/milkymist/s6ddrphy/__init__.py
+++ b/milkymist/s6ddrphy/__init__.py
@@ -1,20 +1,18 @@
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import dfi
 
 class S6DDRPHY(Module):
        def __init__(self, pads):
-               self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2)
+               self.dfi = dfi.Interface(flen(pads.a), flen(pads.ba), 2*flen(pads.dq), 2)
                self.clk4x_wr_strb = Signal()
                self.clk4x_rd_strb = Signal()
 
                ###
 
                inst_items = [
-                       Instance.Parameter("NUM_AD", len(pads.a)),
-                       Instance.Parameter("NUM_BA", len(pads.ba)),
-                       Instance.Parameter("NUM_D", 2*len(pads.dq)),
+                       Instance.Parameter("NUM_AD", flen(pads.a)),
+                       Instance.Parameter("NUM_BA", flen(pads.ba)),
+                       Instance.Parameter("NUM_D", 2*flen(pads.dq)),
 
                        Instance.Input("sys_clk", ClockSignal()),
                        Instance.Input("clk2x_270", ClockSignal("sys2x_270")),

diff --git a/milkymist/timer/__init__.py b/milkymist/timer/__init__.py
index 81c36f1cc9f65b1420b544795570d8ac7c7d8f01..3d1ab705c61b4a61a7d8fd7ff9ca86673fab70d3 100644 (file)
--- a/milkymist/timer/__init__.py
+++ b/milkymist/timer/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index 2fcb19d5f672465157245171709fbfe0f41bffa4..25530d626e8afc6698f8a719695dfe32a2b39a52 100644 (file)
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.bank.eventmanager import *

diff --git a/tb/asmicon/asmicon.py b/tb/asmicon/asmicon.py
index 6daafd91f9570b04994ac99c0fc234557a39c0d4..399a18b381ef217c0616cd500bd0edb13424d1bf 100644 (file)
--- a/tb/asmicon/asmicon.py
+++ b/tb/asmicon/asmicon.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

diff --git a/tb/asmicon/asmicon_wb.py b/tb/asmicon/asmicon_wb.py
index 10e56e8a3b31b85f0bfe6e0d94ba1da18570e5e3..e5efe0f4391074a467bf2376c3cd619bf08763bc 100644 (file)
--- a/tb/asmicon/asmicon_wb.py
+++ b/tb/asmicon/asmicon_wb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus import wishbone, wishbone2asmi, asmibus
 from migen.sim.generic import Simulator, TopLevel
 

diff --git a/tb/asmicon/bankmachine.py b/tb/asmicon/bankmachine.py
index 0221fbd67e27029229bcb4112166700a29fb3b70..fd495d6ecbdb18a77dd16ee0713a5633859b0f4f 100644 (file)
--- a/tb/asmicon/bankmachine.py
+++ b/tb/asmicon/bankmachine.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

diff --git a/tb/asmicon/common.py b/tb/asmicon/common.py
index a9a4b303b21f90c9322332bdaac093ca01b0d7ec..b41956c3f1dcf144c12c73b3e96e5499b8256a67 100644 (file)
--- a/tb/asmicon/common.py
+++ b/tb/asmicon/common.py
@@ -1,7 +1,7 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Proxy
 
 from milkymist import asmicon

diff --git a/tb/asmicon/refresher.py b/tb/asmicon/refresher.py
index a044fcb51901920e73e23431e18b82d8850e2e9b..79b9b18957edaf17e1014ba7d78ac709ed22f80d 100644 (file)
--- a/tb/asmicon/refresher.py
+++ b/tb/asmicon/refresher.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Simulator, TopLevel
 
 from milkymist.asmicon.refresher import *

diff --git a/tb/asmicon/selector.py b/tb/asmicon/selector.py
index 3b99774bdeaede604558397b48389da687376b57..ee987814eadabb0cb5c2f8a89f4807b0824dd094 100644 (file)
--- a/tb/asmicon/selector.py
+++ b/tb/asmicon/selector.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py
index 549ffe0e131a39f1ad8b6ca402f323e080d86b1a..cc38e07e2c130d240e55c53f9c7a0456c6023b59 100644 (file)
--- a/tb/dvisampler/chansync.py
+++ b/tb/dvisampler/chansync.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.sim.generic import *
 
 from milkymist.dvisampler.chansync import ChanSync

diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py
index 76b1f7ac1780b98d8cc728c55204e49da00369cb..bddde1be33dd7ce8e52c44d98d33be463913c63c 100644 (file)
--- a/tb/framebuffer/framebuffer.py
+++ b/tb/framebuffer/framebuffer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus import asmibus
 from migen.sim.generic import Simulator
 

diff --git a/top.py b/top.py
index 3ea99a6f92aa6155b16522ea85a2a62ae83fb75b..1ab79e12d3684a4881bf17d3e932b8a2d377ed21 100644 (file)
--- a/top.py
+++ b/top.py
@@ -2,8 +2,7 @@ from fractions import Fraction
 from math import ceil
 from operator import itemgetter
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 from migen.bank import csrgen