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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 5eb5e15dc0947c5442f6d7f20d58928dcb59ed62..54514b7c59d9cebce59675acaa1dec33656a900c 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -73,7 +73,7 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | - | - | ----- | --- |---------|----------------- |
 |sz |SNZ| 0 RG  |   0 | dz  /   | normal mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
-|sz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
+|zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
 |sz |SNZ| 0 RG  |   1 | SVM /   | subvector reduce mode, SUBVL>1   |
 |sz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |
@@ -81,8 +81,9 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 Fields:
 
 * **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
+* **zz** set both sz and dz equal to this flag
 * **SNZ** when sz=1 and SNZ=1 a value "1" is put in place of zeros when
-  the predicate bit is clear.
+  the predicate bit is clear (on both source and destination masks)
 * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** inverts the Vector Loop order (VL-1 downto 0) rather
 than the normal 0..VL-1