code-comments on divmod2du and maddedu are wrong

RS now defaults to RC in *both* scalar (non-SVP64) and SVP64

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index bb9ffc6e35e9bace3721521ff23a93ded18b49ce..0888f5fbc770ca08133b82ae7a3dd2c833208ce7 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -7,8 +7,8 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- ([0] * 64 || (RC)) + prod
     RT <- sum[64:127]
@@ -27,8 +27,8 @@ VA-Form
 Pseudo-code:
 
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)