radv: do not need to force emit the TCS regs on Vega20

This chip doesn't need the fixup. This fixes a bunch of
dEQP-VK.tessellation tests and avoid random GPU hangs.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index adf158e30e15b44d5539d6f7fd4110be298b47c9..b4a19aa2e5d534bbadb57d787ab485e1c632dbfb 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3691,6 +3691,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                ac_init_exec_full_mask(&ctx.ac);
 
        if (ctx.ac.chip_class == GFX9 &&
+           ctx.ac.family != CHIP_VEGA20 &&
            shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
                ac_nir_fixup_ls_hs_input_vgprs(&ctx);