i965: Program DWord Length in MI_FLUSH_DW
authorAnuj Phogat <anuj.phogat@gmail.com>
Fri, 10 Nov 2017 22:39:17 +0000 (14:39 -0800)
committerAnuj Phogat <anuj.phogat@gmail.com>
Tue, 14 Nov 2017 21:23:18 +0000 (13:23 -0800)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
src/mesa/drivers/dri/i965/brw_pipe_control.c
src/mesa/drivers/dri/i965/intel_blit.c

index bae4ba7c00388c0fd21a911da6240d26430758c1..35f326a5c55da5d51baca91623b1f18976277ff2 100644 (file)
@@ -462,7 +462,7 @@ brw_emit_mi_flush(struct brw_context *brw)
 
    if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
       BEGIN_BATCH_BLT(4);
-      OUT_BATCH(MI_FLUSH_DW);
+      OUT_BATCH(MI_FLUSH_DW | (4 - 2));
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
index 13431a7bd2aec38c50555d5e9cdbbacd74fb84d9..3d7bc92d137bb6317237f26386d5e300530274b8 100644 (file)
@@ -104,7 +104,7 @@ set_blitter_tiling(struct brw_context *brw,
    assert(brw->screen->devinfo.gen >= 6);
 
    /* Idle the blitter before we update how tiling is interpreted. */
-   OUT_BATCH(MI_FLUSH_DW);
+   OUT_BATCH(MI_FLUSH_DW | (4 - 2));
    OUT_BATCH(0);
    OUT_BATCH(0);
    OUT_BATCH(0);