split out reg_table

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index b9707d335296e57f6934ab81438e0d30cf77de06..65e0f373d126ea7c7a4267dacca0b55106397c6e 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -204,22 +204,7 @@ Fields:
 As the above table is a CAM (key-value store) it may be appropriate
 (faster, less gates, implementation-wise) to expand it as follows:
 
-    struct vectorised {
-        bool isvector:1; 
-        int  vew:2; 
-        bool enabled:1;
-        int  predidx:7;  
-    }
-
-    struct vectorised fp_vec[32], int_vec[32];
-
-    for (i = 0; i < len; i++) // from VBLOCK Format
-       tb = int_vec if CSRvec[i].type == 0 else fp_vec
-       idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
-       tb[idx].elwidth  = CSRvec[i].elwidth
-       tb[idx].regidx   = CSRvec[i].regidx  // indirection
-       tb[idx].isvector = CSRvec[i].isvector // 0=scalar
-       tb[idx].enabled  = true;
+[[!inline raw="yes" pages="simple_v_extension/reg_table" ]]
 
 ## Predication Table <a name="predication_csr_table"></a>
 

diff --git a/simple_v_extension/reg_table.mdwn b/simple_v_extension/reg_table.mdwn
new file mode 100644 (file)
index 0000000..b929179
--- /dev/null
+++ b/simple_v_extension/reg_table.mdwn
@@ -0,0 +1,18 @@
+    struct vectorised {
+        bool isvector:1;
+        int  vew:2;
+        int  predidx:7;
+        bool enabled:1;
+    }
+
+    struct vectorised fp_vec[32], int_vec[32];
+
+    for (i = 0; i < len; i++) // from VBLOCK Format
+       tb = int_vec if CSRvec[i].type == 0 else fp_vec
+       idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
+       tb[idx].elwidth  = CSRvec[i].elwidth
+       tb[idx].regidx   = CSRvec[i].regidx  // indirection
+       tb[idx].isvector = CSRvec[i].isvector // 0=scalar
+       tb[idx].enabled  = true;
+
+

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index d59af335ba01e09b924a92be7bc1f0cc87293cce..81e65796edfc9b226edd1ee29c29f5ca5e1b2d03 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -557,14 +557,7 @@ operand size is "over-ridden" in a polymorphic fashion:
 As the above table is a CAM (key-value store) it may be appropriate
 (faster, implementation-wise) to expand it as follows:
 
-    struct vectorised fp_vec[32], int_vec[32];
-
-    for (i = 0; i < len; i++) // from VBLOCK Format
-       tb = int_vec if CSRvec[i].type == 0 else fp_vec
-       idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
-       tb[idx].elwidth  = CSRvec[i].elwidth
-       tb[idx].regidx   = CSRvec[i].regidx  // indirection
-       tb[idx].isvector = CSRvec[i].isvector // 0=scalar
+[[!inline raw="yes" pages="simple_v_extension/reg_table" ]]
 
 ## Predication Table <a name="predication_csr_table"></a>