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add testing
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 22 Mar 2018 12:40:01 +0000
(12:40 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 22 Mar 2018 12:40:01 +0000
(12:40 +0000)
shakti/m_class.mdwn
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a/shakti/m_class.mdwn
b/shakti/m_class.mdwn
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shakti/m_class.mdwn
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shakti/m_class.mdwn
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and accurate PLL clock timing provided, it may become possible to bit-bang
and software-emulate high-speed interfaces such as SATA, HDMI, PCIe and
many more.
+# Testing
+
+* cocotb
+* <https://github.com/aoeldemann/cocotb> cocotb AXI4 stream interface
+
# Research (to investigate)
* <https://level42.ca/projects/ultra64/Documentation/man/pro-man/pro25/index25.1.html>