(define_insn "*fix_truncdfsi2_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
- (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
+ (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f"))
(clobber (match_operand:DI 3 "memory_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
"#"
; because the first makes it clear that operand 0 is not live
; before the instruction.
(define_insn "fctiwz"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
"{fcirz|fctiwz} %0,%1"
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
- (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
+ (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fcfid %0,%1"
[(set_attr "type" "fp")])
(define_insn "fix_truncdfdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fctidz %0,%1"
;; This only is safe if rounding mode set appropriately.
(define_insn_and_split "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
+ (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
(clobber (match_scratch:DF 2 "=f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
"#"
(define_insn_and_split "floatditf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
+ (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
(define_insn_and_split "floatsitf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
+ (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"")
(define_insn_and_split "fix_trunctfdi2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"")
(define_insn_and_split "fix_trunctfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=f")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
(plus:DI (match_dup 0)
(const_int -1)))
(clobber (match_scratch:CC 2 ""))
- (clobber (match_scratch:DI 3 ""))
- (clobber (match_dup 4))])]
+ (clobber (match_scratch:DI 3 ""))])]
"TARGET_POWERPC64"
- "
-{ operands[4] = gen_reg_rtx (DImode); }")
+ "")
;; We need to be able to do this for any operand, including MEM, or we
;; will cause reload to blow up since we don't allow output reloads on
(define_insn "*ctrdi_internal1"
[(set (pc)
- (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal2"
[(set (pc)
- (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
;; Similar, but we can use GE since we have a REG_NONNEG.
(define_insn "*ctrdi_internal3"
[(set (pc)
- (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal4"
[(set (pc)
- (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 0))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
"*
{
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
;; Similar but use EQ
(define_insn "*ctrdi_internal5"
[(set (pc)
- (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal6"
[(set (pc)
- (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+ (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+ (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
(plus:DI (match_dup 1)
(const_int -1)))
- (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
- (clobber (match_scratch:DI 4 "=X,X,r,r"))
- (clobber (match_operand:DI 5 "nonimmediate_operand" "=X,X,X,o"))]
+ (clobber (match_scratch:CC 3 "=X,&x,&x"))
+ (clobber (match_scratch:DI 4 "=X,X,r"))]
"TARGET_POWERPC64"
"*
{
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
- (set_attr "length" "*,12,16,24")])
+ (set_attr "length" "*,12,16")])
;; Now the splitters if we could not allocate the CTR register
(if_then_else (match_operator 2 "comparison_operator"
[(match_operand:DI 1 "gpc_reg_operand" "")
(const_int 1)])
- (match_operand 6 "" "")
- (match_operand 7 "" "")))
+ (match_operand 5 "" "")
+ (match_operand 6 "" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 ""))
- (clobber (match_scratch:DI 4 ""))
- (clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
- "TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))"
+ (clobber (match_scratch:DI 4 ""))]
+ "TARGET_POWERPC64 && reload_completed"
[(parallel [(set (match_dup 3)
(compare:CC (plus:DI (match_dup 1)
(const_int -1))
(set (match_dup 0)
(plus:DI (match_dup 1)
(const_int -1)))])
- (set (pc) (if_then_else (match_dup 8)
- (match_dup 6)
- (match_dup 7)))]
+ (set (pc) (if_then_else (match_dup 7)
+ (match_dup 5)
+ (match_dup 6)))]
"
-{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
+{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
(define_split
(if_then_else (match_operator 2 "comparison_operator"
[(match_operand:DI 1 "gpc_reg_operand" "")
(const_int 1)])
- (match_operand 6 "" "")
- (match_operand 7 "" "")))
+ (match_operand 5 "" "")
+ (match_operand 6 "" "")))
(set (match_operand:DI 0 "nonimmediate_operand" "")
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:CC 3 ""))
- (clobber (match_scratch:DI 4 ""))
- (clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
+ (clobber (match_scratch:DI 4 ""))]
"TARGET_POWERPC64 && reload_completed
&& ! gpc_reg_operand (operands[0], DImode)"
[(parallel [(set (match_dup 3)
(const_int -1)))])
(set (match_dup 0)
(match_dup 4))
- (set (pc) (if_then_else (match_dup 8)
- (match_dup 6)
- (match_dup 7)))]
+ (set (pc) (if_then_else (match_dup 7)
+ (match_dup 5)
+ (match_dup 6)))]
"
-{ operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
+{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
const0_rtx); }")
-(define_split
- [(set (pc)
- (if_then_else (match_operator 2 "comparison_operator"
- [(match_operand:DI 1 "gpc_reg_operand" "")
- (const_int 1)])
- (match_operand 6 "" "")
- (match_operand 7 "" "")))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (plus:DI (match_dup 1)
- (const_int -1)))
- (clobber (match_scratch:CC 3 ""))
- (clobber (match_scratch:DI 4 ""))
- (clobber (match_operand:DI 5 "nonimmediate_operand" ""))]
- "TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))"
- [(set (match_dup 5)
- (match_dup 1))
- (set (match_dup 4)
- (match_dup 5))
- (parallel [(set (match_dup 3)
- (compare:CC (plus:DI (match_dup 4)
- (const_int -1))
- (const_int 0)))
- (set (match_dup 4)
- (plus:DI (match_dup 4)
- (const_int -1)))])
- (set (match_dup 5)
- (match_dup 4))
- (set (match_dup 0)
- (match_dup 5))
- (set (pc) (if_then_else (match_dup 8)
- (match_dup 6)
- (match_dup 7)))]
- "
-{
- operands[8] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
- const0_rtx);
-}")
-
\f
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]