Remove write_verilog call

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index bd7347a19c421f33eaf59e3e6381898cbe92b3dd..99ca4f8d529bed095550179e472729e2b00780aa 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -630,7 +630,7 @@ struct XAigerWriter
                                RTLIL::Selection& sel = holes_module->design->selection_stack.back();
                                sel.select(holes_module);
 
-                               Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v");
+                               Pass::call(holes_module->design, "flatten; aigmap");
 
                                holes_module->design->selection_stack.pop_back();