srrl srli srai etc

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 0b25be0a4c47b9cb76d2d393c741c8314cf4f8a4..276e285fdb43d113aac73304909da0e8328ca84d 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sl(RS1, (RS2 & 0x1F))));
+WRITE_RD(sext32(rv_sl(RS1, rv_and(RS2, sv_reg_t(0x1FU)))));

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 650d333299d07fc5793fc567137850f28b65e718..5d6aeeaea6a2ab58a02d610cf25852f918e79bbb 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-WRITE_RD(rv_lt(sreg_t(RS1), sreg_t(RS2)));
+WRITE_RD(rv_lt(sv_reg_to_sreg(RS1), sv_reg_to_sreg(RS2)));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 216e0eb48e5eae5e5301e96de299bedc35c275fe..b4fd8f07f65c8fffa65441a94c29074114bde4db 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-WRITE_RD(rv_lt(sreg_t(RS1), sreg_t(insn.i_imm())));
+WRITE_RD(rv_lt(sv_reg_to_sreg(RS1), sv_reg_to_sreg(insn.i_imm())));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index a74d2ad8a3ecb7558a859cdb41549d4c5cf557ee..b0d66bd1afe6f790fca0e2b5ce95843e2fee1266 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(rv_lt(RS1, reg_t(insn.i_imm())));
+WRITE_RD(rv_lt(RS1, (insn.i_imm())));

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index f3b4df2ccb1d90431e6c486e69256f599a599f79..5f0586f5493ed749cf9f3a2c61b2ae75186c3fb1 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1,2 @@
-WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), (RS2 & (xlen-1)))));
+WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1),
+                         rv_and(RS2, sv_reg_t(xlen-1)))));

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index f089b5b106e24fc373f8ed1f4a57e39a12884d17..2de77e38000b93ba650b0979a77158df9b666593 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,2 @@
-require(SHAMT < xlen);
+require(rv_lt(SHAMT, sv_reg_t(xlen)));
 WRITE_RD(sext_xlen(rv_sr(sext_xlen(RS1), SHAMT)));

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index ac9832b4631432bbaa85a88f9fa0382c2926d2fe..6c4d3323c0833d56b8edfd76b1aca8a7d3bfcaef 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(int32_t(RS1), SHAMT)));
+WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), SHAMT)));

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index b197770083a08a78d9884634a6662b0146996ffd..ee7c69c51d973cc4f978a0fd323be8bc559b7da2 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr(int32_t(RS1), (RS2 & 0x1F))));
+WRITE_RD(sext32(rv_sr(sv_reg_int32(RS1), rv_and(RS2, sv_reg_t(0x1FU)))));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index c6f92acbd41f7aa975e3b45e7e5d97575b935320..c51d2ad761c264c0049f44f8e7fe933d9149aa25 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1 +1,2 @@
-WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), (RS2 & (xlen-1)))));
+WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1),
+                         rv_and(RS2, sv_reg_t(xlen-1)))));

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index fa4d441c0b692eb3843f855ada5363601314b044..bca4c8356aada577338ee5343a09579ef40491c8 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
-require(SHAMT < xlen);
+require(rv_lt(SHAMT, sv_reg_t(xlen)));
 WRITE_RD(sext_xlen(rv_sr(zext_xlen(RS1), SHAMT)));

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index d2850e47eb1a03fbde51f05aeb394adbcd0b9564..357c72462e974136e2179146bac6318998b86539 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr((uint32_t)RS1, SHAMT)));
+WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1), SHAMT)));

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 45a249471ea1ad954d95aa48c0a24683785269ee..34b574e0f75ea5bc0500dc8811682dbd542eb7e0 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1,2 +1,3 @@
 require_rv64;
-WRITE_RD(sext32(rv_sr((uint32_t)RS1, (RS2 & 0x1F))));
+WRITE_RD(sext32(rv_sr(sv_reg_uint32(RS1),
+                      rv_and(RS2, sv_reg_t(0x1FU)))));