bug 10344: had to move crfternlogi to TLI-Form

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index ae11d5342dd760e51c002ee3e4c34561d364ac39..1b58fc8e00384d32c362b9f6377e73c32995c8b0 100644 (file)
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -157,8 +157,6 @@ X-Form
 
 Pseudo-code:
 
-    a <- CR[BT+32]
-    b <- CR[BA]
     lut <- CR[4*BFB+32:4*BFB+35]
     idx <- CR[BT+32] || CR[BA+32]
     CR[BT+32] <- lut[3-idx]

diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index b5b263e8c48b1b480fa38e06011f10de0240ac5d..d1944212dfbd9741a41b84cbb90311fb9eb6ed33 100644 (file)
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -346,6 +346,7 @@
     |0   |6   |11   |16   |21   |29  |31 |
     | PO | RT |  RA |  RB | TLI | XO |Rc |
     | PO | RT |  RA |  RB | TLI | XO |L  |
+    | PO | BT |  BA |  BB | TLI | XO |/  |
 
 # 1.6.38 MM-FORM
     |0    |6    |11   |16   |21   |24 |25  |31  |
@@ -386,11 +387,11 @@
     BA (11:15)
         Field used to specify a bit in the CR to be used as
         a source.
-        Formats: XL, X
+        Formats: XL, X, TLI
     BB (16:20)
          Field used to specify a bit in the CR to be used as
          a source.
-         Formats: XL
+         Formats: XL, TLI
     BC (21:25)
          Field used to specify a bit in the CR to be used as
          a source.
@@ -447,7 +448,7 @@
     BT (6:10)
          Field used to specify a bit in the CR or in the
          FPSCR to be used as a target.
-         Formats: XL, X
+         Formats: XL, X, TLI
     BX,B (30,16:20)
         Fields that are concatenated to specify a VSR to
         be used as a source.

diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index bb110567773289bca18cfd7eca14416bb74ea97d..1f8ba13f44278db4578f2a33848ef73bb2c43ba7 100644 (file)
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -1,7 +1,11 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
+# ternlog (integer, CR and CR field)
 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
---------010,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------00100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------01100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-------10100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----00001-,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----00101-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BA_BB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+
+# integer butterfly
+-----100100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----101100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----110100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 

diff --git a/src/openpower/insndb/asm.py b/src/openpower/insndb/asm.py
index 8f6ad336d8c6c8e09bb6d21faa47dbd5775c4db1..9797a1e5201e47fd074c527bbed79d3f457bc702 100644 (file)
--- a/src/openpower/insndb/asm.py
+++ b/src/openpower/insndb/asm.py
@@ -313,7 +313,9 @@ if __name__ == '__main__':
         #"sv.cmp/ff=gt *0,*1,*2,0",
         #"dsld 5,4,5,3",
         "crfbinlog 3,4,5,15",
-        #"crbinlog 3,4,5",
+        "crbinlog 3,4,5",
+        "crfternlogi 3,4,5,149,5",
+        "crternlogi 3,4,5,149",
     ]
     isa = SVP64Asm(lst, macros=macros)
     log("list:\n", "\n\t".join(list(isa)))

diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index eacdfeb88b8ca647fad93b70fa52eb8f9e86c7c6..5df82a7f5b83ff3b4ec1e701ff17edc2ea1a24f0 100644 (file)
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -48,6 +48,20 @@ def ternlogi(rc, rt, ra, rb, imm):
     return expected
 
 
+def crfternlogi(bf, bfa, bfb, imm, mask):
+    expected = bf&~mask # start at BF, mask overwrites masked bits only
+    checks = (bfb, bfa, bf) # LUT positions 1<<0=bfb 1<<1=bfa 1<<2=bf
+    for i in range(4):
+        lut_index = 0
+        for j, check in enumerate(checks):
+            if check & (1<<i):
+                lut_index |= 1<<j
+        maskbit = (mask >> i) & 0b1
+        if (imm & (1<<lut_index)) and maskbit:
+            expected |= 1<<i
+    return expected
+
+
 class BitManipTestCase(TestAccumulatorBase):
     def case_gbbd(self):
         lst = ["gbbd 0, 1"]
@@ -78,17 +92,7 @@ class BitManipTestCase(TestAccumulatorBase):
 
         lst = list(SVP64Asm(lst, bigendian))
         e = ExpectedState(pc=4)
-        expected = bf&~mask # start at BF, mask overwrites masked bits only
-        checks = (bfb, bfa, bf) # LUT positions 1<<0=bfb 1<<1=bfa 1<<2=bf
-        for i in range(4):
-            lut_index = 0
-            for j, check in enumerate(checks):
-                if check & (1<<i):
-                    lut_index |= 1<<j
-            maskbit = (mask >> i) & 0b1
-            if (imm & (1<<lut_index)) and maskbit:
-                expected |= 1<<i
-        e.crregs[3] = expected
+        e.crregs[3] = crfternlogi(bf, bfa, bfb, imm, mask)
         e.crregs[4] = bfa
         e.crregs[5] = bfb
         self.add_case(Program(lst, bigendian), initial_regs=None, expected=e,
@@ -102,7 +106,6 @@ class BitManipTestCase(TestAccumulatorBase):
 
     def case_crfternlogi_random(self):
         for i in range(100):
-            rc = bool(hash_256(f"crfternlogi rc {i}") & 1)
             imm = hash_256(f"crfternlogi imm {i}") & 0xFF
             bf = hash_256(f"crfternlogi bf {i}") % 2 ** 4
             bfa = hash_256(f"crfternlogi bfa {i}") % 2 ** 4