[AArch64] Prefer FPRs over GPRs for INSR

INSR of GPRs involves a cross-file move while INSR of FPRs doesn't.
We should therefore disparage the GPR version relative to the FPR
version.

The patch also adds MOVPRFX handling, but this is only tested
properly by the ACLE.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add
	MOVPRFX alternatives.  Make the GPR alternatives more expensive
	than the FPR ones.

gcc/testsuite/
	* gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into
	a temporary FPR.

From-SVN: r274192

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31cbd59c4b67bf03f9079f1f738bacc5b69b71d4..ef6c201e29fe0a5021fc799b5c58b511d279a9f3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add
+       MOVPRFX alternatives.  Make the GPR alternatives more expensive
+       than the FPR ones.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/aarch64-sve.md (fold_extract_last_<mode>):

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 41c92a01babcd1dc5b0decb6e132d329b78710d3..baba7318f20f9324f3d0774088a617e8ead9bfbc 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -835,15 +835,18 @@
 
 ;; Shift an SVE vector left and insert a scalar into element 0.
 (define_insn "vec_shl_insert_<mode>"
-  [(set (match_operand:SVE_ALL 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_ALL 0 "register_operand" "=?w, w, ??&w, ?&w")
        (unspec:SVE_ALL
-         [(match_operand:SVE_ALL 1 "register_operand" "0, 0")
-          (match_operand:<VEL> 2 "register_operand" "rZ, w")]
+         [(match_operand:SVE_ALL 1 "register_operand" "0, 0, w, w")
+          (match_operand:<VEL> 2 "aarch64_reg_or_zero" "rZ, w, rZ, w")]
          UNSPEC_INSR))]
   "TARGET_SVE"
   "@
    insr\t%0.<Vetype>, %<vwcore>2
-   insr\t%0.<Vetype>, %<Vetype>2"
+   insr\t%0.<Vetype>, %<Vetype>2
+   movprfx\t%0, %1\;insr\t%0.<Vetype>, %<vwcore>2
+   movprfx\t%0, %1\;insr\t%0.<Vetype>, %<Vetype>2"
+  [(set_attr "movprfx" "*,*,yes,yes")]
 )
 
 ;; -------------------------------------------------------------------------

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dd37b72aedae5de731e3e8ff4bcb342d87a41b98..22cf0e97c125ef58cfce69b212238dd47b18db94 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into
+       a temporary FPR.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * gcc.target/aarch64/sve/clastb_8.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
index cbf418e4e6313f640587fc187b8f4740864750fe..bc698ddd38d5efb949ec808a3c0b3b89c23f75db 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
@@ -10,12 +10,13 @@ typedef int32_t vnx4si __attribute__((vector_size (32)));
 
 /*
 ** foo:
+**     fmov    (s[0-9]+), w1
 **     mov     (z[0-9]+\.s), w2
 **     mov     (z[0-9]+\.s), w0
-**     insr    \2, w1
-**     insr    \2, w1
-**     insr    \2, w1
-**     zip1    \2, \2, \1
+**     insr    \3, \1
+**     insr    \3, \1
+**     insr    \3, \1
+**     zip1    \3, \3, \2
 **     ...
 */
 __attribute__((noipa))