Clean up some whitepsace outliers

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index b0528d473fbc3e3a686b0333aa11d8c99837ce06..274177a684e023f14415dd75e050c5e7bb989366 100644 (file)
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -660,8 +660,8 @@ struct DfflibmapPass : public Pass {
                map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_");
                map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_");
 
-               log("  final dff cell mappings:\n");
-               logmap_all();
+               log("  final dff cell mappings:\n");
+               logmap_all();
 
                for (auto &it : design->modules_)
                        if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index ddbd7bf5d84fc6affd803f3735504871e15f0b18..0b7931e480c0dc015cd542e778ca0ccacd9b2b63 100644 (file)
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -132,9 +132,9 @@ static void dump_dot_graph(string filename,
                            pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
                            pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
                            std::function<GraphStyle(RTLIL::SigBit)> node_style =
-                                       [](RTLIL::SigBit) { return GraphStyle{}; },
+                                   [](RTLIL::SigBit) { return GraphStyle{}; },
                            std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
-                                       [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
+                                   [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
                            string name = "")
 {
        FILE *f = fopen(filename.c_str(), "w");

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb189264396e4080e74eab398779583ea..f27540bd7f10e5116ebb6290ecacc4a21777f894 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
        input RAD0, RAD1, RAD2, RAD3,
        output DO0, DO1
 );
-       parameter WCKMUX = "WCK";
+       parameter WCKMUX = "WCK";
        parameter WREMUX = "WRE";
        parameter INITVAL_0 = 16'h0000;
        parameter INITVAL_1 = 16'h0000;
@@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
        input [3:0] RAD,
        output [3:0] DO
 );
-       parameter WCKMUX = "WCK";
+       parameter WCKMUX = "WCK";
        parameter WREMUX = "WRE";
        parameter [63:0] INITVAL = 64'h0000000000000000;