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Updated TODOs
authorClifford Wolf <clifford@clifford.at>
Sun, 24 Nov 2013 16:58:05 +0000 (17:58 +0100)
committerClifford Wolf <clifford@clifford.at>
Sun, 24 Nov 2013 16:58:05 +0000 (17:58 +0100)
README patch | blob | history

diff --git a/README b/README
index 2277ef129f210ba996d830f023499e618578821d..9406896895da238c5a7e4796a4556560b7bbb086 100644 (file)
--- a/README
+++ b/README
@@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Technology mapping for real-world applications
-   - Add "mini synth script" feature to techmap pass
-   - Add const-folding via cell parameters to techmap pass
+   - Add bit-wise const-folding via cell parameters to techmap pass
    - Rewrite current stdcells.v techmap rules (modular and clean)
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)