Add latch test modified from #1363

diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
new file mode 100644 (file)
index 0000000..83bad7f
--- /dev/null
+++ b/tests/xilinx/latches.v
@@ -0,0 +1,58 @@
+module latchp
+    ( input d, en, output reg q );
+       always @*
+               if ( en )
+                       q <= d;
+endmodule
+
+module latchn
+    ( input d, en, output reg q );
+       always @*
+               if ( !en )
+                       q <= d;
+endmodule
+
+module latchsr
+    ( input d, en, clr, pre, output reg q );
+       always @*
+               if ( clr )
+                       q <= 1'b0;
+               else if ( pre )
+                       q <= 1'b1;
+               else if ( en )
+                       q <= d;
+endmodule
+
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2
+);
+
+
+latchp u_latchp (
+        .en (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+
+latchn u_latchn (
+        .en (clk ),
+        .d (a ),
+        .q (b1 )
+    );
+
+
+latchsr u_latchsr (
+        .en (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b2 )
+    );
+
+endmodule

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
new file mode 100644 (file)
index 0000000..ac11028
--- /dev/null
+++ b/tests/xilinx/latches.ys
@@ -0,0 +1,15 @@
+read_verilog latches.v
+
+proc
+flatten
+equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+async2sync
+equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+design -load preopt
+synth_xilinx
+cd top
+select -assert-count 1 t:LUT1
+select -assert-count 2 t:LUT3
+select -assert-count 3 t:LDCE
+select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D