soc/integration/soc_core: avoid removing uart interrupts (break some designs)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 0a9c98b693f561cc2604a75e22b438fab41dd3f3..e2dd457fe7177a8710074a24028bec9c30bbb887 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -145,8 +145,8 @@ class SoCCore(Module):
             else:
                 self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
                 self.submodules.uart = uart.UART(self.uart_phy)
-        else:
-            del self.soc_interrupt_map["uart"]
+        #else:
+        #    del self.soc_interrupt_map["uart"]
 
         if ident:
             if ident_version: