struct iris_screen *screen,
struct iris_vtable *vtbl,
struct pipe_debug_callback *dbg,
- uint8_t ring)
+ uint8_t engine)
{
batch->screen = screen;
batch->vtbl = vtbl;
batch->dbg = dbg;
- /* ring should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
- assert((ring & ~I915_EXEC_RING_MASK) == 0);
- assert(util_bitcount(ring) == 1);
- batch->ring = ring;
+ /* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
+ assert((engine & ~I915_EXEC_RING_MASK) == 0);
+ assert(util_bitcount(engine) == 1);
+ batch->engine = engine;
batch->exec_count = 0;
batch->exec_array_size = 100;
.buffer_count = batch->exec_count,
.batch_start_offset = 0,
.batch_len = batch->primary_batch_size,
- .flags = batch->ring |
+ .flags = batch->engine |
I915_EXEC_NO_RELOC |
I915_EXEC_BATCH_FIRST |
I915_EXEC_HANDLE_LUT,
uint32_t hw_ctx_id;
- /** Which ring this batch targets - a I915_EXEC_RING_MASK value */
- uint8_t ring;
+ /** Which engine this batch targets - a I915_EXEC_RING_MASK value */
+ uint8_t engine;
/** The validation list */
struct drm_i915_gem_exec_object2 *validation_list;
}
// XXX: compute support
-#define IS_COMPUTE_PIPELINE(batch) (batch->ring != I915_EXEC_RENDER)
+#define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
/**
* Emit a series of PIPE_CONTROL commands, taking into account any