add means to run an external core from a verilog file.

basically turns soc.vhdl (etc) into a mini general-purpose fabric
interconnect (oh and allows Libre-SOC to use it)

diff --git a/Makefile b/Makefile
index 820bd71f4d97d5d5ffaece199599bcdc3489c0a7..a3a32b84c4e9fab7f39399a6114951de63dc5bd7 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -50,10 +50,12 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
        loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
        core.vhdl fpu.vhdl
 
-soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
+_soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
        wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
        spi_rxtx.vhdl spi_flash_ctrl.vhdl
 
+soc_files = $(core_files) $(_soc_files)
+
 uart_files = $(wildcard uart16550/*.v)
 
 soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
@@ -139,6 +141,7 @@ endif
 # Hello world
 MEMORY_SIZE=8192
 RAM_INIT_FILE=hello_world/hello_world.hex
+SIM_MAIN_BRAM=true
 
 # Micropython
 #MEMORY_SIZE=393216
@@ -148,6 +151,7 @@ RAM_INIT_FILE=hello_world/hello_world.hex
 #MEMORY_SIZE=536870912
 #RAM_INIT_FILE=dtbImage.microwatt.hex
 #SIM_MAIN_BRAM=false
+#SIM_BRAM_CHAINBOOT=5242880 # 0x500000
 #SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
 FPGA_TARGET ?= ORANGE-CRAB
@@ -176,9 +180,6 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
-GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
-       -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
-       -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT)
 
 
 clkgen=fpga/clk_gen_ecp5.vhd
@@ -195,11 +196,26 @@ endif
 FPGA_MAIN_BRAM=fpga/main_bram.vhdl
 #FPGA_MAIN_BRAM=
 
-fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
+_fpga_files = fpga/soc_reset.vhdl \
        fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd $(FPGA_MAIN_BRAM) \
        nonrandom.vhdl
 
-synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+# use an alternative core (in verilog)
+EXTERNAL_CORE=true
+ifeq ($(EXTERNAL_CORE),false)
+    fpga_files = $(_fpga_files) $(_soc_files) $(core_files)
+    synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+else
+    util_files = decode_types.vhdl common.vhdl wishbone_types.vhdl utils.vhdl \
+                core_dummy.vhdl
+    fpga_files = $(_fpga_files) $(_soc_files)
+    synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+endif
+
+GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
+       -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
+       -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) \
+       -gEXTERNAL_CORE=$(EXTERNAL_CORE)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
@@ -208,6 +224,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
+# --top-module toplevel
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
        verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT # --trace
        make -C obj_dir -f Vmicrowatt.mk

diff --git a/core_dummy.vhdl b/core_dummy.vhdl
new file mode 100644 (file)
index 0000000..ae5d49b
--- /dev/null
+++ b/core_dummy.vhdl
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+
+entity core is
+    generic (
+        SIM : boolean := false;
+       DISABLE_FLATTEN : boolean := false;
+        EX1_BYPASS : boolean := true;
+        HAS_FPU : boolean := true;
+        HAS_BTC : boolean := true;
+       RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+       ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0');
+        LOG_LENGTH : natural := 512
+        );
+    port (
+        clk          : in std_ulogic;
+        rst          : in std_ulogic;
+
+       -- Alternate reset (0xffff0000) for use by DRAM init fw
+       alt_reset    : in std_ulogic;
+
+       -- Wishbone interface
+        wishbone_insn_in  : in wishbone_slave_out;
+        wishbone_insn_out : out wishbone_master_out;
+
+        wishbone_data_in  : in wishbone_slave_out;
+        wishbone_data_out : out wishbone_master_out;
+
+       dmi_addr        : in std_ulogic_vector(3 downto 0);
+       dmi_din         : in std_ulogic_vector(63 downto 0);
+       dmi_dout        : out std_ulogic_vector(63 downto 0);
+       dmi_req         : in std_ulogic;
+       dmi_wr          : in std_ulogic;
+       dmi_ack         : out std_ulogic;
+
+       ext_irq         : in std_ulogic;
+
+       terminated_out   : out std_logic
+        );
+end core;
+
+architecture behave of core is
+begin
+
+end behave;

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 98ebeb22e0367c75d2b4eeec87c32dcbbb21332f..6c23dd70f2a1c3cb3d971da41d1c7f7084cc970e 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -10,6 +10,7 @@ entity toplevel is
        MEMORY_SIZE   : positive := (384*1024);
        RAM_INIT_FILE : string   := "firmware.hex";
        RESET_LOW     : boolean  := true;
+       EXTERNAL_CORE     : boolean  := false;
        SIM_MAIN_BRAM     : boolean  := false;
        SIM_BRAM_CHAINBOOT  : positive  := 0;
        CLK_INPUT     : positive := 100000000;
@@ -82,6 +83,7 @@ begin
            MEMORY_SIZE   => MEMORY_SIZE,
            SIM_BRAM_CHAINBOOT  => SIM_BRAM_CHAINBOOT,
            SIM_MAIN_BRAM   => SIM_MAIN_BRAM,
+           EXTERNAL_CORE   => EXTERNAL_CORE,
            RAM_INIT_FILE => RAM_INIT_FILE,
            SIM           => false,
            CLK_FREQ      => CLK_FREQUENCY,

diff --git a/soc.vhdl b/soc.vhdl
index 1c3599eda152fd476d5593dda48247885532598f..9ab2babd177505f4de515a4f8cffbf569afda9e2 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -56,6 +56,7 @@ entity soc is
         HAS_FPU            : boolean := true;
         HAS_BTC            : boolean := true;
        DISABLE_FLATTEN_CORE : boolean := false;
+       EXTERNAL_CORE : boolean := false;
        HAS_DRAM           : boolean  := false;
        SIM_MAIN_BRAM      : boolean  := false;
        SIM_BRAM_CHAINBOOT      : positive  := 0;
@@ -248,6 +249,27 @@ architecture behaviour of soc is
         dcd_pad_i   : in std_ulogic
         );
     end component;
+
+    -- use this for external processor core (e.g. mycore.v, not core.vhdl)
+    component external_core_top port (
+        clk          : in std_ulogic;
+        rst          : in std_ulogic;
+        alt_reset    : in std_ulogic;
+        wishbone_insn_in  : in wishbone_slave_out;
+        wishbone_insn_out : out wishbone_master_out;
+
+        wishbone_data_in  : in wishbone_slave_out;
+        wishbone_data_out : out wishbone_master_out;
+        dmi_addr    : in std_ulogic_vector(3 downto 0);
+        dmi_din         : in std_ulogic_vector(63 downto 0);
+        dmi_dout    : out std_ulogic_vector(63 downto 0);
+        dmi_req         : in std_ulogic;
+        dmi_wr      : in std_ulogic;
+        dmi_ack         : out std_ulogic;
+        ext_irq     : in std_ulogic;
+        terminated_out   : out std_logic
+        );
+    end component;
 begin
 
     resets: process(system_clk)
@@ -266,6 +288,7 @@ begin
     end process;
 
     -- Processor core
+    processor_internal: if not EXTERNAL_CORE generate
     processor: entity work.core
        generic map(
            SIM => SIM,
@@ -292,6 +315,27 @@ begin
            dmi_req => dmi_core_req,
            ext_irq => core_ext_irq
            );
+    end generate;
+
+    processor_external: if EXTERNAL_CORE generate
+       processor: external_core_top
+       port map(
+           clk => system_clk,
+           rst => rst_core,
+           alt_reset => alt_reset_d,
+           wishbone_insn_in => wishbone_icore_in,
+           wishbone_insn_out => wishbone_icore_out,
+           wishbone_data_in => wishbone_dcore_in,
+           wishbone_data_out => wishbone_dcore_out,
+           dmi_addr => dmi_addr(3 downto 0),
+           dmi_dout => dmi_core_dout,
+           dmi_din => dmi_dout,
+           dmi_wr => dmi_wr,
+           dmi_ack => dmi_core_ack,
+           dmi_req => dmi_core_req,
+           ext_irq => core_ext_irq
+           );
+    end generate;
 
     -- Wishbone bus master arbiter & mux
     wb_masters_out <= (0 => wishbone_dcore_out,