anv/pipeline: Get rid of the kernel pointer fields

Now that we have anv_shader_bin, they're completely redundant with other
information we have in the pipeline.  For vertex shaders, we also go
through way too much work to put the offset in one or the other field and
then look at which one we put it in later.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bdc2f01351f25d6ea70206c05b4f200ee34d1931..bdac404dca721011fef41383dc72b7e5890c156f 100644 (file)
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -488,17 +488,6 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
       ralloc_free(mem_ctx);
    }
 
-   const struct brw_vs_prog_data *vs_prog_data =
-      (const struct brw_vs_prog_data *)bin->prog_data;
-
-   if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
-      pipeline->vs_simd8 = bin->kernel.offset;
-      pipeline->vs_vec4 = NO_KERNEL;
-   } else {
-      pipeline->vs_simd8 = NO_KERNEL;
-      pipeline->vs_vec4 = bin->kernel.offset;
-   }
-
    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
 
    return VK_SUCCESS;
@@ -576,8 +565,6 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
       ralloc_free(mem_ctx);
    }
 
-   pipeline->gs_kernel = bin->kernel.offset;
-
    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
 
    return VK_SUCCESS;
@@ -700,8 +687,6 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
       ralloc_free(mem_ctx);
    }
 
-   pipeline->ps_ksp0 = bin->kernel.offset;
-
    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
 
    return VK_SUCCESS;
@@ -773,8 +758,6 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
       ralloc_free(mem_ctx);
    }
 
-   pipeline->cs_simd = bin->kernel.offset;
-
    anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
 
    return VK_SUCCESS;
@@ -1024,11 +1007,6 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
     */
    memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
 
-   pipeline->vs_simd8 = NO_KERNEL;
-   pipeline->vs_vec4 = NO_KERNEL;
-   pipeline->gs_kernel = NO_KERNEL;
-   pipeline->ps_ksp0 = NO_KERNEL;
-
    pipeline->active_stages = 0;
 
    const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 30deb02e1da59b17928e3a8e92a5a03ef9ad2c2f..24035f4a41f2e90b91a9d9b782df101369d5b4ae 100644 (file)
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1389,11 +1389,6 @@ struct anv_pipeline {
 
    VkShaderStageFlags                           active_stages;
    struct anv_state                             blend_state;
-   uint32_t                                     vs_simd8;
-   uint32_t                                     vs_vec4;
-   uint32_t                                     ps_ksp0;
-   uint32_t                                     gs_kernel;
-   uint32_t                                     cs_simd;
 
    uint32_t                                     vb_used;
    uint32_t                                     binding_stride[MAX_VBS];

diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index b54610c072ceb9f1b3c8e861828bf8229999519a..57d44773e77c958932ccad9d2775898cd098581c 100644 (file)
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -106,14 +106,14 @@ genX(graphics_pipeline_create)(
       gen7_emit_vs_workaround_flush(brw);
 #endif
 
-   if (pipeline->vs_vec4 == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs);
    } else {
       const struct anv_shader_bin *vs_bin =
          pipeline->shaders[MESA_SHADER_VERTEX];
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
-         vs.KernelStartPointer         = pipeline->vs_vec4;
+         vs.KernelStartPointer         = vs_bin->kernel.offset;
 
          vs.ScratchSpaceBasePointer = (struct anv_address) {
             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
@@ -139,14 +139,14 @@ genX(graphics_pipeline_create)(
 
    const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 
-   if (pipeline->gs_kernel == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
    } else {
       const struct anv_shader_bin *gs_bin =
          pipeline->shaders[MESA_SHADER_GEOMETRY];
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
-         gs.KernelStartPointer         = pipeline->gs_kernel;
+         gs.KernelStartPointer         = gs_bin->kernel.offset;
 
          gs.ScratchSpaceBasePointer = (struct anv_address) {
             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
@@ -184,7 +184,7 @@ genX(graphics_pipeline_create)(
       }
    }
 
-   if (pipeline->ps_ksp0 == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
@@ -205,8 +205,8 @@ genX(graphics_pipeline_create)(
    } else {
       const struct anv_shader_bin *fs_bin =
          pipeline->shaders[MESA_SHADER_FRAGMENT];
-
       const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
+
       if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
           wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
          anv_finishme("two-sided color needs sbe swizzling setup");
@@ -216,9 +216,10 @@ genX(graphics_pipeline_create)(
       emit_3dstate_sbe(pipeline);
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
-         ps.KernelStartPointer0           = pipeline->ps_ksp0;
+         ps.KernelStartPointer0           = fs_bin->kernel.offset;
          ps.KernelStartPointer1           = 0;
-         ps.KernelStartPointer2           = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
+         ps.KernelStartPointer2           = fs_bin->kernel.offset +
+                                            wm_prog_data->prog_offset_2;
 
          ps.ScratchSpaceBasePointer = (struct anv_address) {
             .bo = anv_scratch_pool_alloc(device, &device->scratch_pool,

diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index 10cef64fcbab687c5c7a0fe5f1fd942512132050..20fd4ba0f9bb5f79882a3e87d55c403b45f300cb 100644 (file)
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -109,11 +109,11 @@ genX(graphics_pipeline_create)(
          wm.EarlyDepthStencilControl         = NORMAL;
       }
 
-      wm.BarycentricInterpolationMode = pipeline->ps_ksp0 == NO_KERNEL ?
-         0 : wm_prog_data->barycentric_interp_modes;
+      wm.BarycentricInterpolationMode =
+         wm_prog_data ? wm_prog_data->barycentric_interp_modes : 0;
    }
 
-   if (pipeline->gs_kernel == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
    } else {
       const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
@@ -125,7 +125,7 @@ genX(graphics_pipeline_create)(
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
          gs.SingleProgramFlow       = false;
-         gs.KernelStartPointer      = pipeline->gs_kernel;
+         gs.KernelStartPointer      = gs_bin->kernel.offset;
          gs.VectorMaskEnable        = false;
          gs.SamplerCount            = get_sampler_count(gs_bin);
          gs.BindingTableEntryCount  = get_binding_table_entry_count(gs_bin);
@@ -177,10 +177,7 @@ genX(graphics_pipeline_create)(
    offset = 1;
    length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 
-   uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
-                                                         pipeline->vs_vec4;
-
-   if (vs_start == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
          vs.FunctionEnable = false;
          /* Even if VS is disabled, SBE still gets the amount of
@@ -193,7 +190,7 @@ genX(graphics_pipeline_create)(
          pipeline->shaders[MESA_SHADER_VERTEX];
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
-         vs.KernelStartPointer            = vs_start;
+         vs.KernelStartPointer            = vs_bin->kernel.offset;
          vs.SingleVertexDispatch          = false;
          vs.VectorMaskEnable              = false;
 
@@ -222,7 +219,8 @@ genX(graphics_pipeline_create)(
 
          vs.MaximumNumberofThreads        = devinfo->max_vs_threads - 1;
          vs.StatisticsEnable              = false;
-         vs.SIMD8DispatchEnable           = pipeline->vs_simd8 != NO_KERNEL;
+         vs.SIMD8DispatchEnable           =
+            vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
          vs.VertexCacheDisable            = false;
          vs.FunctionEnable                = true;
 
@@ -236,7 +234,7 @@ genX(graphics_pipeline_create)(
    }
 
    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
-   if (pipeline->ps_ksp0 == NO_KERNEL) {
+   if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
          extra.PixelShaderValid = false;
@@ -248,9 +246,10 @@ genX(graphics_pipeline_create)(
       emit_3dstate_sbe(pipeline);
 
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
-         ps.KernelStartPointer0     = pipeline->ps_ksp0;
+         ps.KernelStartPointer0     = fs_bin->kernel.offset;
          ps.KernelStartPointer1     = 0;
-         ps.KernelStartPointer2     = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
+         ps.KernelStartPointer2     = fs_bin->kernel.offset +
+                                      wm_prog_data->prog_offset_2;
          ps._8PixelDispatchEnable   = wm_prog_data->dispatch_8;
          ps._16PixelDispatchEnable  = wm_prog_data->dispatch_16;
          ps._32PixelDispatchEnable  = false;

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 2bc7e7473a36aab6e0314b4b55e3b387374b425d..a77973cc28efd9d276d0504f9234218fbb7afc55 100644 (file)
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1364,10 +1364,12 @@ flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
 
    const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
 
+   const struct anv_shader_bin *cs_bin =
+      pipeline->shaders[MESA_SHADER_COMPUTE];
    struct anv_state state =
       anv_state_pool_emit(&device->dynamic_state_pool,
                           GENX(INTERFACE_DESCRIPTOR_DATA), 64,
-                          .KernelStartPointer = pipeline->cs_simd,
+                          .KernelStartPointer = cs_bin->kernel.offset,
                           .BindingTablePointer = surfaces.offset,
                           .BindingTableEntryCount = 0,
                           .SamplerStatePointer = samplers.offset,

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2d5c62e2a9cabd8e7bce37893b47497417f98083..edab197d7f771304e890613f3e735e3540c97ed9 100644 (file)
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -68,10 +68,6 @@ compute_pipeline_create(
     */
    memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
 
-   pipeline->vs_simd8 = NO_KERNEL;
-   pipeline->vs_vec4 = NO_KERNEL;
-   pipeline->gs_kernel = NO_KERNEL;
-
    pipeline->active_stages = 0;
 
    pipeline->needs_data_cache = false;

diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index b30be1443db70019d87a0ce7bfa461bc6fc098af..18b4877b958c3c0f1359a34d073572325e696137 100644 (file)
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -366,10 +366,10 @@ emit_3dstate_sbe(struct anv_pipeline *pipeline)
    const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
    const struct brw_vue_map *fs_input_map;
 
-   if (pipeline->gs_kernel == NO_KERNEL)
-      fs_input_map = &vs_prog_data->base.vue_map;
-   else
+   if (gs_prog_data)
       fs_input_map = &gs_prog_data->base.vue_map;
+   else
+      fs_input_map = &vs_prog_data->base.vue_map;
 
    struct GENX(3DSTATE_SBE) sbe = {
       GENX(3DSTATE_SBE_header),