fhdl/verilog: do not attempt to initialize instance and mem output signals

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index f6326e74842c0b5652c9c272122a67edf755ccba..fa4c4ae4d49c241ca5edfdb8a033d5e44e07bc35 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -220,9 +220,13 @@ def _printmemories(f, ns, handler, clk):
                r += handler(memory, ns, clk)
        return r
 
-def _printinit(f, exclude, ns):
+def _printinit(f, ios, ns):
        r = ""
-       signals = list_signals(f) - exclude - list_targets(f)
+       signals = list_signals(f) \
+               - ios \
+               - list_targets(f) \
+               - list_inst_ios(f, False, True, False) \
+               - list_mem_ios(f, False, True)
        if signals:
                r += "initial begin\n"
                for s in signals: