cpu/profile.cc
dev/alpha_console.cc
+ dev/disk_image.cc
dev/io_device.cc
+ dev/platform.cc
+ dev/simconsole.cc
+ dev/simple_disk.cc
+ dev/uart.cc
+ dev/uart8250.cc
kern/kernel_binning.cc
kern/kernel_stats.cc
''')
# dev/baddev.cc
-# dev/simconsole.cc
-# dev/disk_image.cc
# dev/etherbus.cc
# dev/etherdump.cc
# dev/etherint.cc
# dev/pcidev.cc
# dev/pcifake.cc
# dev/pktfifo.cc
-# dev/platform.cc
# dev/sinic.cc
-# dev/simple_disk.cc
# dev/tsunami.cc
# dev/tsunami_cchip.cc
# dev/isa_fake.cc
# dev/tsunami_io.cc
# dev/tsunami_pchip.cc
-# dev/uart.cc
-# dev/uart8250.cc
if env['TARGET_ISA'] == 'alpha':
full_system_sources += Split('''
class UnimpFault : public AlphaFault
{
-#if FULL_SYSTEM
private:
std::string panicStr;
static FaultName _name;
UnimpFault(std::string _str)
: panicStr(_str)
{ }
-#endif
+
FaultName name() {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
AlphaConsole::AlphaConsole(Params *p)
: BasicPioDevice(p), disk(p->disk),
- console(params()->cons), system(params()->sys), cpu(params()->cpu)
+ console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
{
pioSize = sizeof(struct AlphaAccess);
Tick
AlphaConsole::read(Packet &pkt)
{
- pkt.time = curTick + pioDelay;
/** XXX Do we want to push the addr munging to a bus brige or something? So
* the device has it's physical address and then the bridge adds on whatever
assert(pkt.result == Unknown);
assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+
+ pkt.time = curTick + pioDelay;
Addr daddr = pkt.addr - pioAddr;
uint32_t *data32;
p->pio_delay = pio_latency;
p->cons = sim_console;
p->disk = disk;
- p->sys = system;
+ p->alpha_sys = system;
+ p->system = system;
p->cpu = cpu;
return new AlphaConsole(p);
}
{
SimConsole *cons;
SimpleDisk *disk;
- AlphaSystem *sys;
+ AlphaSystem *alpha_sys;
BaseCPU *cpu;
};
protected:
class Platform;
class PioDevice;
class DmaDevice;
+class System;
/**
* The PioPort class is a programmed i/o port that all devices that are
{
std::string name;
Platform *platform;
+ System *system;
};
protected:
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
-#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "dev/simple_disk.hh"
-#include "mem/functional/physical.hh"
+#include "mem/port.hh"
#include "sim/builder.hh"
+#include "sim/system.hh"
using namespace std;
-SimpleDisk::SimpleDisk(const string &name, PhysicalMemory *pmem,
- DiskImage *img)
- : SimObject(name), physmem(pmem), image(img)
+SimpleDisk::SimpleDisk(const string &name, System *sys, DiskImage *img)
+ : SimObject(name), system(sys), image(img)
{}
SimpleDisk::~SimpleDisk()
void
SimpleDisk::read(Addr addr, baddr_t block, int count) const
{
- uint8_t *data = physmem->dma_addr(addr, count);
- if (!data)
- panic("dma out of range! read addr=%#x count=%d\n", addr, count);
+ uint8_t *data = new uint8_t[SectorSize * count];
if (count & (SectorSize - 1))
panic("Not reading a multiple of a sector (count = %d)", count);
for (int i = 0, j = 0; i < count; i += SectorSize, j++)
image->read(data + i, block + j);
+ system->functionalPort.writeBlob(addr, data, count);
+
DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
DDUMP(SimpleDiskData, data, count);
+
+ delete data;
}
void
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
- SimObjectParam<PhysicalMemory *> physmem;
+ SimObjectParam<System *> system;
SimObjectParam<DiskImage *> disk;
END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
- INIT_PARAM(physmem, "Physical Memory"),
+ INIT_PARAM(system, "System pointer"),
INIT_PARAM(disk, "Disk Image")
END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
CREATE_SIM_OBJECT(SimpleDisk)
{
- return new SimpleDisk(getInstanceName(), physmem, disk);
+ return new SimpleDisk(getInstanceName(), system, disk);
}
REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)
#include "arch/isa_traits.hh"
class DiskImage;
-class PhysicalMemory;
+class System;
/*
* Trivial interface to a disk image used by the System Console
typedef uint64_t baddr_t;
protected:
- PhysicalMemory *physmem;
+ System *system;
DiskImage *image;
public:
- SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
+ SimpleDisk(const std::string &name, System *sys, DiskImage *img);
~SimpleDisk();
void read(Addr addr, baddr_t block, int count) const;
*/
/** @file
- * Implements a 8250 UART
+ * Implements a base class for UARTs
*/
-#include <string>
-#include <vector>
-
-#include "base/inifile.hh"
-#include "base/str.hh" // for to_number
-#include "base/trace.hh"
#include "dev/simconsole.hh"
#include "dev/uart.hh"
#include "dev/platform.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
-Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
- Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
- : PioDevice(name, p), addr(a), size(s), cons(c)
+Uart::Uart(Params *p)
+ : BasicPioDevice(p), platform(p->platform), cons(p->cons)
{
- mmu->add_child(this, RangeSize(addr, size));
-
-
- if (bus) {
- pioInterface = newPioInterface(name, hier, bus, this,
- &Uart::cacheAccess);
- pioInterface->addAddrRange(RangeSize(addr, size));
- pioLatency = pio_latency * bus->clockRate;
- }
status = 0;
platform->uart = this;
}
-Tick
-Uart::cacheAccess(MemReqPtr &req)
-{
- return curTick + pioLatency;
-}
-
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
#include "dev/io_device.hh"
class SimConsole;
-class MemoryController;
class Platform;
const int RX_INT = 0x1;
const int TX_INT = 0x2;
-class Uart : public PioDevice
+class Uart : public BasicPioDevice
{
protected:
int status;
- Addr addr;
- Addr size;
+ Platform *platform;
SimConsole *cons;
public:
- Uart(const std::string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
- Platform *p);
-
- virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
- virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
+ struct Params : public BasicPioDevice::Params
+ {
+ SimConsole *cons;
+ };
+ Uart(Params *p);
/**
* Inform the uart that there is data available.
*/
bool intStatus() { return status ? true : false; }
- /**
- * Return how long this access will take.
- * @param req the memory request to calcuate
- * @return Tick when the request is done
- */
- Tick cacheAccess(MemReqPtr &req);
+ protected:
+ const Params *params() const {return (const Params *)_params; }
+
};
#endif // __UART_HH__
#include "dev/simconsole.hh"
#include "dev/uart8250.hh"
#include "dev/platform.hh"
-#include "mem/bus/bus.hh"
-#include "mem/bus/pio_interface.hh"
-#include "mem/bus/pio_interface_impl.hh"
-#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
using namespace std;
}
-Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *pio_bus,
- Tick pio_latency, Platform *p)
- : Uart(name, c, mmu, a, s, hier, pio_bus, pio_latency, p),
- txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
+Uart8250::Uart8250(Params *p)
+ : Uart(p), txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
+ pioSize = 8;
+
IER = 0;
DLAB = 0;
LCR = 0;
MCR = 0;
-
}
-Fault
-Uart8250::read(MemReqPtr &req, uint8_t *data)
+Tick
+Uart8250::read(Packet &pkt)
{
- Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
+ assert(pkt.result == Unknown);
+ assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
+ assert(pkt.size == 1);
+
+ pkt.time = curTick + pioDelay;
+ Addr daddr = pkt.addr - pioAddr;
+ uint8_t *data;
+
DPRINTF(Uart, " read register %#x\n", daddr);
- assert(req->size == 1);
+ if (!pkt.data) {
+ data = new uint8_t;
+ pkt.data = data;
+ } else
+ data = pkt.data;
switch (daddr) {
case 0x0:
if (cons->dataAvailable())
cons->in(*data);
else {
- *(uint8_t*)data = 0;
+ *data = 0;
// A limited amount of these are ok.
DPRINTF(Uart, "empty read of RX register\n");
}
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
- *(uint8_t*)data = IER;
+ *data = IER;
} else { // DLM divisor latch MSB
;
}
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
if (status & RX_INT) /* Rx data interrupt has a higher priority */
- *(uint8_t*)data = IIR_RXID;
+ *data = IIR_RXID;
else if (status & TX_INT)
- *(uint8_t*)data = IIR_TXID;
+ *data = IIR_TXID;
else
- *(uint8_t*)data = IIR_NOPEND;
+ *data = IIR_NOPEND;
//Tx interrupts are cleared on IIR reads
status &= ~TX_INT;
break;
case 0x3: // Line Control Register (LCR)
- *(uint8_t*)data = LCR;
+ *data = LCR;
break;
case 0x4: // Modem Control Register (MCR)
break;
if (cons->dataAvailable())
lsr = UART_LSR_DR;
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
- *(uint8_t*)data = lsr;
+ *data = lsr;
break;
case 0x6: // Modem Status Register (MSR)
- *(uint8_t*)data = 0;
+ *data = 0;
break;
case 0x7: // Scratch Register (SCR)
- *(uint8_t*)data = 0; // doesn't exist with at 8250.
+ *data = 0; // doesn't exist with at 8250.
break;
default:
panic("Tried to access a UART port that doesn't exist\n");
break;
}
- return NoFault;
-
+ return pioDelay;
}
-Fault
-Uart8250::write(MemReqPtr &req, const uint8_t *data)
+Tick
+Uart8250::write(Packet &pkt)
{
- Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
- DPRINTF(Uart, " write register %#x value %#x\n", daddr, *(uint8_t*)data);
+ assert(pkt.result == Unknown);
+ assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
+ assert(pkt.size == 1);
+
+ pkt.time = curTick + pioDelay;
+ Addr daddr = pkt.addr - pioAddr;
+
+ uint8_t *data = pkt.data;
+
+ DPRINTF(Uart, " write register %#x value %#x\n", daddr, *data);
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- cons->out(*(uint8_t *)data);
+ cons->out(*data);
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
- IER = *(uint8_t*)data;
+ IER = *data;
if (UART_IER_THRI & IER)
{
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
case 0x2: // FIFO Control Register (FCR)
break;
case 0x3: // Line Control Register (LCR)
- LCR = *(uint8_t*)data;
+ LCR = *data;
break;
case 0x4: // Modem Control Register (MCR)
- if (*(uint8_t*)data == (UART_MCR_LOOP | 0x0A))
+ if (*data == (UART_MCR_LOOP | 0x0A))
MCR = 0x9A;
break;
case 0x7: // Scratch Register (SCR)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
- return NoFault;
+ return pioDelay;
}
void
}
+void
+Uart8250::addressRanges(AddrRangeList &range_list)
+{
+ assert(pioSize != 0);
+ range_list.clear();
+ range_list.push_back(RangeSize(pioAddr, pioSize));
+}
+
void
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
- SimObjectParam<SimConsole *> console;
- SimObjectParam<MemoryController *> mmu;
- SimObjectParam<Platform *> platform;
Param<Addr> addr;
- Param<Addr> size;
- SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
- SimObjectParam<HierParams *> hier;
-
+ SimObjectParam<Platform *> platform;
+ SimObjectParam<SimConsole *> sim_console;
+ SimObjectParam<System *> system;
END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
- INIT_PARAM(console, "The console"),
- INIT_PARAM(mmu, "Memory Controller"),
- INIT_PARAM(platform, "Pointer to platfrom"),
INIT_PARAM(addr, "Device Address"),
- INIT_PARAM_DFLT(size, "Device size", 0x8),
- INIT_PARAM(pio_bus, ""),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
+ INIT_PARAM(platform, "platform"),
+ INIT_PARAM(sim_console, "The Simulator Console"),
+ INIT_PARAM(system, "system object")
END_INIT_SIM_OBJECT_PARAMS(Uart8250)
CREATE_SIM_OBJECT(Uart8250)
{
- return new Uart8250(getInstanceName(), console, mmu, addr, size, hier,
- pio_bus, pio_latency, platform);
+ Uart8250::Params *p = new Uart8250::Params;
+ p->name = getInstanceName();
+ p->pio_addr = addr;
+ p->pio_delay = pio_latency;
+ p->platform = platform;
+ p->cons = sim_console;
+ p->system = system;
+ return new Uart8250(p);
}
REGISTER_SIM_OBJECT("Uart8250", Uart8250)
+
* Defines a 8250 UART
*/
-#ifndef __TSUNAMI_UART_HH__
-#define __TSUNAMI_UART_HH__
+#ifndef __DEV_UART8250_HH__
+#define __DEV_UART8250_HH__
#include "dev/tsunamireg.h"
#include "base/range.hh"
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
class SimConsole;
-class MemoryController;
class Platform;
class Uart8250 : public Uart
IntrEvent rxIntrEvent;
public:
- Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
- Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
- Platform *p);
+ Uart8250(Params *p);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Tick read(Packet &pkt);
+ virtual Tick write(Packet &pkt);
+ virtual void addressRanges(AddrRangeList &range_list);
/**
// downstream from this bus, yes? That is, the union of all
// the 'owned' address ranges of all the other interfaces on
// this bus...
- virtual void addressRanges(AddrRangeList &range_list, bool &owner);
+ virtual void addressRanges(AddrRangeList &resp, AddrRangeList &snoop);
// Hack to make translating port work without changes
virtual int deviceBlockSize() { return 32; }
}
void
-PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
- bool &owner)
+PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
{
- memory->getAddressRanges(range_list, owner);
+ memory->getAddressRanges(resp, snoop);
}
void
-PhysicalMemory::getAddressRanges(AddrRangeList &range_list, bool &owner)
+PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
{
- owner = true;
- range_list.clear();
- range_list.push_back(RangeSize(base_addr, pmem_size));
+ snoop.clear();
+ resp.clear();
+ resp.push_back(RangeSize(base_addr, pmem_size));
}
int
class SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
- physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+ system = Param.System(Parent.any, "Sysetm Pointer")
#include "config/full_system.hh"
#include "cpu/exec_context.hh"
#include "mem/page_table.hh"
-#include "mem/mem_object.hh"
+#include "mem/physical.hh"
#include "mem/translating_port.hh"
#include "sim/builder.hh"
#include "sim/process.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "mem/mem_object.hh"
+#include "mem/physical.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "arch/vtophys.hh"
#include "base/remote_gdb.hh"
#include "kern/kernel_stats.hh"
-#include "mem/physical.hh"
#endif
using namespace std;
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
- SimObjectParam<MemObject *> physmem;
+ SimObjectParam<PhysicalMemory *> physmem;
END_DECLARE_SIM_OBJECT_PARAMS(System)
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