# Instructions
-**DRAFT** Both `madded` and `msubed` are VA-Form:
+**DRAFT**
+
+The pseudocode for `msubed RT, RA, RB, RC`` is:
+
+ prod[0:127] = (RA) * (RB)
+ sub[0:127] = EXTZ(RC) - prod
+ RT <- sub[64:127]
+ RS <- sub[0:63] # RS is either RC or RT+VL
+
+Note that RC is not sign-extended to 64-bit. In a Vector Loop
+it contains the top half of the previous multiply-with-subtract,
+and the current product must be subtracted from it.
+
+
+Both `madded` and `msubed` are VA-Form:
|0.....5|6..10|11..15|16..20|21..25|26..31|
|-------|-----|------|------|------|------|